AVX512 Instructions Help

[waylaa]

I am trying to re-write a C++ project that heavily uses AVX512 because of the Keccak algorithm in C#, and these are the instructions that it uses:

_mm512_maskz_loadu_epi64
_mm512_ternarylogic_epi64
_mm512_permutexvar_epi64
_mm512_permutex2var_epi64
_mm512_rol_epi64
_mm512_rolv_epi64
_mm512_xor_si512
_mm512_unpacklo_epi64
_mm512_unpackhi_epi6
_mm512_mask_blend_epi64
_mm512_mask_blend_epi64
_mm512_mask_storeu_epi64
_mm512_maskz_set1_epi64
_mm512_setr_epi64

I cannot find most of them. Are some of them missing? I would appreciate any help.

[tannergooding]

C Intrinsic	.NET API	Notes
_mm512_maskz_loadu_epi64	Avx512F.MaskLoad
_mm512_ternarylogic_epi64	Avx512F.TernaryLogic	.NET 9 has support for recognizing many x op y op z patterns and emitting ternary logic implicitly
_mm512_permutexvar_epi64	Avx512F.PermuteVar8x64
_mm512_permutex2var_epi64	Avx512F.PermuteVar8x64x2
_mm512_rol_epi64	Avx512F.RotateLeft
_mm512_rolv_epi64	Avx512F.RotateLeftVariable
_mm512_xor_si512	Avx512F.Xor	Just use x ^ y instead
_mm512_unpacklo_epi64	Avx512F.UnpackLow
_mm512_unpackhi_epi6	Avx512F.UnpackHigh
_mm512_mask_blend_epi64	Avx512F.BlendVariable	Alternatively just use Vector512.ConditionalSelect
_mm512_mask_storeu_epi64	Avx512F.MaskStore	Not exposed yet, was missed due to requiring more complex mask support
_mm512_maskz_set1_epi64	N/A	Long term this will be supported via ConditionalSelect(mask, Vector512.Create(value), Vector512.Zero)
_mm512_setr_epi64	Vector512.Create(...)	We don't expose set, only setr as it makes sense to pass parameters from element 0 to element count

In general masking support is not done in the same way as it's done in C/C++. Instead, we internally track whether something is a mask or not and continue exposing everything as a Vector512<T>. This helps immensely when writing cross platform code or code that needs to support multiple ISAs (SSE2, SSE4.1, AVX2, AVX512, AVX10, etc) as the code and general masking concepts are consistent. We then pattern match usages like ConditionalSelect(mask, x + y, merge) to emit a masked x + y instruction on hardware that supports it and otherwise to emit the natural fallback (which would be to use something like the add; blendv sequence instead).

For places that have different behavior when a mask is used and therefore cannot be pattern matched (like maskz_loadu) we will eventually expose explicit APIs that take in the mask as a Vector512<T> (or appropriately sized vector). If that input is actually a mask, then you get the optimal codegen as expected. We didn't land the full support in .NET 8 simply due to the sheer size/scope of AVX512 support; it is something we have partially landed in .NET 9 so far and are continuing to work on. -- It's also worth noting that in general masked instructions are more expensive than unmasked instructions and so you still want to be selective with how such code is used. You still in most scenarios want to restrict masking primarily to outside our core loop only when handling leading or trailing elements if at all possible (which it should be for most algorithms).

[tannergooding]

If this is done in a hot loop then the indices should get hoisted.

That being said, if this is being done in a hot loop and you explicitly know the common case is less than 64-bytes, then masking may not be what you want for perf regardless. The masked loads have implicitly higher cost and in tight loops can sometimes lead to a 4x or worse perf decrease compared to the alternatives. The optimization guides go over this and suggest measuring against scenarios like doing parallel loads of the smaller data parts and explicitly blending them together (often 1 cycle, no more than 2 cycles post the load cost; vs the masked load which messes with forwarding, forces a dependency, etc).

[nietras]

The optimization guides go over this

Yeah, unfortunately I can never find anything in the +5000 page long Intel Optimization Manual 😅 I think loading via normal register will be slower in this case too. But good suggestions. If I was sure no issue with page faults loading full v512 length and then masking/and that would be more optimal yes. I am probably just disappointed (again) that ISA has poor support for mask generation or similar ... 😁

[nietras]

One nit, it would be nice if loads e.g. also had ref overloads so one can avoid having to pin.

[tannergooding]

In most cases you should just be using the xplat APIs instead.

There are a handful of cases, such as Gather/Scatter and MaskLoad/Store, however, that don't have ref based alternatives. I'd be "ok" with a proposal for those, but noting they need an Unsafe suffix and potentially an overload that takes an index parameter as well.

They are not valid for cases like LoadAligned where the data must be pinned, since it could otherwise move out from under you.

[nietras]

Yeah I use the xplat ref based in general for load/store