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  • Wuhan University of Science and Technology
  • Wuhan University of Science and Technology

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  1. AES_128 AES_128 Public

    Verilog 1

  2. AES_IP_FPGA AES_IP_FPGA Public

    This project aims to design and implement an efficient AES-128 encryption IP core for FPGA platforms using Verilog, featuring pipelined architecture, custom IP interfaces, and optimized resource ut…

    VHDL

  3. E203_ZYNQ_FPGA E203_ZYNQ_FPGA Public

    The Hummingbird E203 hbirdv2 project was replicated and ported to ZYNQ7020

    Verilog