Update SIMD shuffle instruction

Signed-off-by: HyukWoo Park <[email protected]>
clover2123 · Oct 31, 2023 · e764cf5 · e764cf5
1 parent 73c7772
commit e764cf5
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Showing 6 changed files with 1,326 additions and 2 deletions.
diff --git a/src/interpreter/ByteCode.h b/src/interpreter/ByteCode.h
@@ -494,7 +494,8 @@ class FunctionType;
 #define FOR_EACH_BYTECODE_SIMD_ETC_OP(F) \
     F(V128BitSelect)                     \
     F(V128Load32Zero)                    \
-    F(V128Load64Zero)
+    F(V128Load64Zero)                    \
+    F(I8X16Shuffle)
 
 #define FOR_EACH_BYTECODE(F)                   \
     FOR_EACH_BYTECODE_OP(F)                    \
@@ -1685,6 +1686,33 @@ class V128Load64Zero : public MemoryLoad {
 #endif
 };
 
+class I8X16Shuffle : public ByteCode {
+public:
+    I8X16Shuffle(ByteCodeStackOffset src0, ByteCodeStackOffset src1, ByteCodeStackOffset dst, uint8_t* value)
+        : ByteCode(Opcode::I8X16ShuffleOpcode)
+        , m_srcOffsets{ src0, src1 }
+        , m_dstOffset(dst)
+    {
+        ASSERT(!!value);
+        memcpy(m_value, value, 16);
+    }
+
+    const ByteCodeStackOffset* srcOffsets() const { return m_srcOffsets; }
+    ByteCodeStackOffset dstOffset() const { return m_dstOffset; }
+    const uint8_t* value() const { return m_value; }
+
+#if !defined(NDEBUG)
+    void dump(size_t pos)
+    {
+        printf("I8X16Shuffle src0: %" PRIu32 " src1: %" PRIu32 " dst: %" PRIu32, (uint32_t)m_srcOffsets[0], (uint32_t)m_srcOffsets[1], (uint32_t)m_dstOffset);
+    }
+#endif
+protected:
+    ByteCodeStackOffset m_srcOffsets[2];
+    ByteCodeStackOffset m_dstOffset;
+    uint8_t m_value[16];
+};
+
 class TableGet : public ByteCode {
 public:
     TableGet(uint32_t index, ByteCodeStackOffset srcOffset, ByteCodeStackOffset dstOffset)

diff --git a/src/interpreter/Interpreter.cpp b/src/interpreter/Interpreter.cpp
@@ -1050,6 +1050,24 @@ ByteCodeStackOffset* Interpreter::interpret(ExecutionState& state,
         NEXT_INSTRUCTION();
     }
 
+    DEFINE_OPCODE(I8X16Shuffle)
+        :
+    {
+        using Type = typename SIMDType<uint8_t>::Type;
+        I8X16Shuffle* code = (I8X16Shuffle*)programCounter;
+        Type sel;
+        memcpy(sel.v, code->value(), 16);
+        auto lhs = readValue<Type>(bp, code->srcOffsets()[0]);
+        auto rhs = readValue<Type>(bp, code->srcOffsets()[1]);
+        Type result;
+        for (uint8_t i = 0; i < Type::Lanes; i++) {
+            result[i] = sel[i] < Type::Lanes ? lhs[sel[i]] : rhs[sel[i] - Type::Lanes];
+        }
+        writeValue<Type>(bp, code->dstOffset(), result);
+        ADD_PROGRAM_COUNTER(I8X16Shuffle);
+        NEXT_INSTRUCTION();
+    }
+
     DEFINE_OPCODE(MemorySize)
         :
     {

diff --git a/src/parser/WASMParser.cpp b/src/parser/WASMParser.cpp
@@ -1936,6 +1936,17 @@ class WASMBinaryReader : public wabt::WASMBinaryReaderDelegate {
         }
     }
 
+    virtual void OnSimdShuffleOpExpr(int opcode, uint8_t* value) override
+    {
+        ASSERT(static_cast<WASMOpcode>(opcode) == WASMOpcode::I8X16ShuffleOpcode);
+        ASSERT(peekVMStackSize() == Walrus::valueSizeInStack(toValueKind(Type::V128)));
+        auto src1 = popVMStack();
+        ASSERT(peekVMStackSize() == Walrus::valueSizeInStack(toValueKind(Type::V128)));
+        auto src0 = popVMStack();
+        auto dst = pushVMStack(WASMCodeInfo::codeTypeToMemorySize(g_wasmCodeInfo[opcode].m_resultType));
+        pushByteCode(Walrus::I8X16Shuffle(src0, src1, dst, value), WASMOpcode::I8X16ShuffleOpcode);
+    }
+
     void generateBinaryCode(WASMOpcode code, size_t src0, size_t src1, size_t dst)
     {
         switch (code) {