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[WIP] Verible standalone preprocessor #1360

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Commits on Jul 21, 2022

  1. Configuration menu
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  2. constructing the control flow tree, to enable the preprocessor tool t…

    …o generate all variants with the new mode generate-variants
    karimtera committed Jul 21, 2022
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  3. applying clang-format

    karimtera committed Jul 21, 2022
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  4. Configuration menu
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Commits on Jul 22, 2022

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Commits on Jul 25, 2022

  1. Adding a new common util class.

    "verible::CmdPositionalArguments" class only supports these types so far: SV files, +define+<name>[=<value>], and +incdir+<dir>.
    karimtera committed Jul 25, 2022
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  2. fixing clang-tidy errors

    karimtera committed Jul 25, 2022
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  3. Changes:

    - Adding an interface function "AddDefineFromCmdLine" to use the macro added by +define+<foo> argument to "VerilogPreprocess".
    karimtera committed Jul 25, 2022
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Commits on Jul 27, 2022

  1. Changes done:

    - Added a feature to VerilogPreprocess which allows to store paths,
      That can be used later to find the SV file to include.
    - The preprocessor tool takes these paths from the user,
      as a +incdir+<path>[+<another_path>] and set then in VerilogPreprocess.
    - The included files macros and conditionals can be expanded and evaluated.
    - Some limitations exists and were written as TODOs in place,
      need to open issues for these.
    karimtera committed Jul 27, 2022
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Commits on Jul 29, 2022

  1. Changes done:

    - The preprocessor tool preserves the white-spaces in the SV files.
    - Changed the output of the -generate_variants and -multipecu from tokens (enum,text) into normal text.
    karimtera committed Jul 29, 2022
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  2. using run-clang-format.sh

    karimtera committed Jul 29, 2022
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Commits on Aug 12, 2022

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