Skip to content

Chisel v6.0.0-M3

Pre-release
Pre-release
Compare
Choose a tag to compare
@jackkoenig jackkoenig released this 25 Aug 05:28
· 1181 commits to main since this release
v6.0.0-M3
e6418eb
This commit was created on GitHub.com and signed with GitHub’s verified signature. The key has expired.
GPG key ID: 4AEE18F83AFDEB23
Expired
Verified
Learn about vigilant mode.

Features

  • Make it possible to illegalize .asUInt on OpaqueTypes (by @jackkoenig in #3344)
    Subclasses of OpaqueType can override errorOnAsUInt to make it an elaboration time error if .asUInt is called on an instance of the particular type (including when nested inside of an Aggregate). This closes a large loophole in the OpaqueType API.
  • Add MuxCell intrinsics (by @uenoku in #3372)
    This commit adds new intrinsics (MuxCell2 and MuxCell4) to provide users a way to directly use 2-to-1 and 4-to-1 MUX cells in synthesis tools (currently synopsys and cadence are supported) from Chisel level. Appropriate pragmas will be annotated in output verilog. FIRRTL implementation is llvm/circt#5428
  • SRAM API: Add a parameter to initialize the memory (by @jared-barocsi in #3364)
    SRAM.apply and SRAM.masked now take a contents parameter, by default a None, which is a string path to a binary file on the filesystem which the SRAM should be initialized with.
  • Support literals and DontCare in DataView targets (by @jackkoenig in #3389)
  • SRAM API: Add multiple-clocked port API (by @jared-barocsi in #3383)
    Add new SRAM APIs that take three Clock sequences as parameters instead of the number of read/write/read-write ports. This will sequentially instantiate a memory port for each clock in the Clock sequence and drive them accordingly.
  • Add a new take method on Bits that returns the requested number (by @chick in #3402)
    take will accept an argument of zero and will return a zero-length UInt
  • Add support for configurable warnings (by @jackkoenig in #3414)
    Add support for configurable warnings, see https://www.chisel-lang.org/chisel3/docs/explanations/warnings.html
  • Support leading whitespace in --warn-conf-file (by @jackkoenig in #3438)
    • Also make line comments work on lines with filter-action pairs.
  • Add FirtoolBinaryPath option (by @GeorgeLyon in #3434)
    • Add FirtoolBinaryPathOption to select a different firtool binary at runtime.
  • Add --dump-fir option to ChiselStage (by @jackkoenig in #3453)
    This option will dump the .fir before invoking firtool.
  • Additional changes:
    • Use os.lib for invoking firtool
    • Use lazy serialization to avoid holding the entire FIRRTL in memory.
    • Mix NoStackTrace into FirtoolNotFound
    • Fix detection of no firtool
  • Module.clockOption and Module.resetOption return Option[Clock] and Option[Reset]
  • Add Boolean Property type (by @adkian-sifive in #3503)
    API Modification: Add Boolean support to Property API
  • Implement CIRCT converter (by @SpriteOvO in #3466)
  • Add Disable, a new API for disabling simulation constructs (by @jackkoenig in #3497)
    Disable is a new type that represents the concept of disabling a simulation construct. It is handled similarly to the implicit clock and reset except Disable is notionally a function of the current implicit reset. Its default value is "not has been reset", a two-state simulation-only construct that is 0 when simulation starts and only becomes 1 after reset has been asserted, and then de-asserted. Because Disable has simulation-only semantics, it is not a Data and can only be used by simulation-only APIs.

API Modification

  • Error when calling .viewAs on non-hardware (by @jackkoenig in #3398)
  • Add a new BaseType type that Data inherits, and use it for ports. (by @mikeurbach in #3429)
  • Make LTL properties use Clock and Disable by default (by @jackkoenig in #3498)
    Properties in package chisel3.ltl will now be clocked and disabled by default (if there is an implicit clock and disable). Default disable is not hasBeenReset of the current implicit reset (if one exists). The clock and disable can be removed by setting them to None via withClock, withReset, and withDisable APIs.

API Deprecation

  • Deprecate calling .viewAs on non-hardware (by @jackkoenig in #3395)
    Also fix a crash that could occur when viewing a non-Data containing non-hardware Data.
  • Deprecate old BoringUtils API (by @jared-barocsi in #3428)
    BoringUtils.bore(source, sinks), BoringUtils.addSource and BoringUtils.addSink are now deprecated in favor of the new BoringUtils APIs: BoringUtils.bore(source), BoringUtils.tap(source) ...

Backend Code Generation

  • [codegen] Use FIRRTL 3.0.0 syntax (connect, invalidate, regreset, radix-encoded integer literals) (by @seldridge in #3188)
  • [codegen] Emit literal identifiers for numeric ids (by @seldridge in #3374)
    Use FIRRTL 3.0.0 emission of literal identifiers when a Chisel name begins with a digit.
  • Support bulk connection for const types (by @trilorez in #3384)
  • Avoid emitting 'const const' for const vecs of const elements (by @trilorez in #3393)
    Multiple consecutive 'const' modifiers are no longer emitted when emitting a const vector of const elements.
  • Update BoringUtils.bore to not add a port when boring from a port. (by @mikeurbach in #3411)
  • update ChiselPlugin to name tuples (by @albertchen-sifive in #3436)
    The chisel plugin will now name wires that are part of tuples e.g. val x = (Wire(Bool()), Wire(Bool())) will generate wires with names x_1 and x_2

Performance

  • Fix issue where reify would do the same lookup twice (by @jackkoenig in #3392)
  • Optimize source locator escaping when emitting FIRRTL (by @jackkoenig in #3439)
    Only escape/unescape source locators that need it, avoids a String copy in the common case.
  • Use Instantiate for LTL intrinsic instantiation (by @jackkoenig in #3499)
    This vastly reduces the IR size when using LTL properties

Fixes

  • Correctly set ProbeInfo to None for Aggregate types on a probe.read (by @girishpai in #3382)
    Probe.read needs to return non-probe data to work with connection operators. Previous version of this was not handling aggregates correctly - this PR rectifies that.
  • Add messages to require statements in Math (by @jackkoenig in #3385)
    • log2 functions
    • unsignedBitLength
  • [svsim] Don't redirect simulation stderr to a pipe (by @GeorgeLyon in #3403)
    • Fixes an issue where simulations that logged to stderr could hang
  • Sanitize Record._elements (by @jackkoenig in #3419)
    Fixes a bug in D/I where unsanitary names would lead to a crash. It also makes the Printable output for Bundles and Records use the sanitary names which makes them better match the FIRRTL.
  • Extend constants in probe.force and probe.forceInitial methods. (by @debs-sifive in #3418)
    Properly extend forced values in probe.force and probe.forceInitial methods. Error out on unknown widths.
  • Remove SourceLineNoCol (by @jackkoenig in #3433)
    Tweak emission of source locators in error messages to match format in emitting FIRRTL (removed the : between filename and line number).
  • Remove intermediate wire creation from Boringutils Tap API (by @debs-sifive in #3441)
    Remove intermediate wire creation from Boringutils Tap API. Force/release statements on these taps will now force/release the intended signal, rather than the intermediate wire.
  • Restore BundleUpcastable (by @sequencer in #3487)
    Restore BundleUpcastable and deprecate it.
  • BoringUtils: rwprobe from inside module, test (rw)taps of IO's. (by @dtzSiFive in #3485)
    RWTaps are done from inside the module instead of externally, for compatibility.
    Add tests for taps and rw-taps of IO's.

Documentation

  • README.md: Fix link to gitter badge (by @smarter in #3370)
  • Add Chips Alliance to README (by @jackkoenig in #3377)
  • Update suggested milestones in PULL_REQUEST_TEMPLATE.md (by @mwachs5 in #3394)
    Update the PULL REQUEST TEMPLATE to prompt for 6.0 and 5.0.x milestones
  • Update versioning.md for Chisel 5.0.0. (by @jackkoenig in #3421)
    Describe new use of SemVer and update older text that applies to only Chisel 3.0-3.6.
  • [docs] Fix chiseltest version in old compatible versions (by @jackkoenig in #3448)
  • [docs] Update naming explanation for newer firtool (by @jackkoenig in #3454)

Dependency Updates

Build and Internal Changes

  • Add tests for interfaces with reference ports (by @debs-sifive in #3303)
  • Add test demonstrating a ref to an aggregate member (by @trilorez in #3369)
  • Split out MixedVecSpec integration tests (by @jackkoenig in #3373)
  • Un-ignore force tests now we have newer verilator in CI. (by @dtzSiFive in #3378)
  • upgrade mill to 0.11.0 (by @sequencer in #3367)
  • Disable argument extensions when in devcontainer (by @GeorgeLyon in #3409)
    • VSCode's Metal's Test Explorer UI can now run tests when the CHISEL_ARGUMENT_EXTENSIONS environment variable is set to DISABLE
  • Remove firrtl/regress, these old files are unused (by @jackkoenig in #3413)
  • Move more Data methods to BaseType and base connection checks on BaseType. (by @mikeurbach in #3442)
    MonoConnect.elemConnect is updated to accept any BaseType, so its checks can be re-used for any source and sink BaseType that are already known to be compatible.
  • [ci] Use 'default' as version string for typical CIRCT version (by @jackkoenig in #3467)
    Make it such that using "Install CIRCT" does not require specifying a CIRCT version, instead using the string 'default' as a way to pick the "default version". The "default version" is the version that Chisel is tested and released against.
  • Tests for RWTapping aggregates (by @debs-sifive in #3443)

Full Changelog: v6.0.0-M2...v6.0.0-M3

Contributors

smarter, chick, and 16 other contributors
Assets 4
Loading