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Chisel v3.4.0
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@chick chick released this 07 Oct 00:17
v3.4.0
c643817

Highlights

  • A new Chisel compiler plug-in significantly improves generated names (#1448)

Generated names can be automatically prefixed with names based on their use and scope. Users
have new options to control naming. These names will be more stable as changes are made to generators.

  • There is a new basic model checking API (#1499)

Adds assert(), assume(), cover() statements to a new chisel3.experimental.verification library.
These statements generate their FIRRTL counterparts, which in turn emit their Verilog counterparts.
Note that only SystemVerilog's immediate statements are supported.
These new statements form the foundation of a new model checking interface that may be extended in future releases.

Deprecations

  • Move LFSR16 to Compatibility Mode (Deprecated in 3.2), - Remove deprecated LFSR16 utility (#1476)
  • Deprecate Module.io and BlackBox.io virtual methods (future 2.13 compatibility) (#1550)
  • Remove use of deprecated PreservesAll, cleanup dependencies, all phases are converted to be more canonical in there specification of dependencies (#1558)
  • Restore and deprecate Chisel.Driver, until we also remove underlying chisel3.Driver (#1571)
  • Bump 'removed in 3.3' deprecations to 3.4 (#1439)
  • Remove Deprecated Usages of chisel3.Driver, CircuitForm (#1481)
  • (#1551) Deprecate support for Scala 2.11

API Modification

  • Better Building of FIRRTL From Source, Use sbt-sriracha for firrtl and treadle source deps (#1563)

  • Add new annotation for Chisel Circuit serialization, --chisel-output-file is added to the ChiselCli. (#1580)

Fixes

  • Relax plugin scalac phase order (#1568)

  • Switch to HowToSerialize for Emission (#1405)

    Fix emit{Firrtl,Verilog} for CustomFileEmission
    Change ChiselStage helper methods for emitting FIRRTL (emitFirrtl) and
    Verilog (emitVerilog) to look for Circuit and Verilog annotations
    instead of DeletedAnnotations. This is needed after migrating to the
    CustomFileEmission mixin in FIRRTL where FIRRTL will no longer delete
    emitter annotations.

  • update Select.get(IntermediateAnd)Leafs to work with records (#1525)

  • Allow a counter to be manually reset (#1527)

  • Check whether signals escape their when scopes, Include and check when scoping as part of reg/mem/wire/node bindings (#1518)

  • bug fix for build.sc (#1579)

Feature

  • Allow a counter to be instantiated using a Scala range (#1515)
  • Canonicalize construction of Decoupled with no payload (#785)
  • Memoize the hashcode of the ChiselCircuitAnnotation, improves performance of multi-phase generators (#1485)
  • Grouping Chisel API, added a chisel annotation API for triggering the firrtl.transforms.GroupComponents transformation. (#1073)
  • Add support for ScalaFix. (#1203)
  • Provide an implementation of litOption() for BundleLits (#1280)
  • Chisel3 can use treadle to run tests (faster), only depends on Treadle dependency in tests (#1554)
  • make parameters for util modules public (#1452)
  • Recursively generate one-hot multiplexers for aggregates (#1557)
  • Move multi-clock to explanations (#1561)
  • Add ChiselPhase, Stop writing files in ChiselStage$ methods, Expand ChiselStage$ helpers (#1566)
  • Add chisel plugin to mill build system. This enables better, more stable naming capabilities in Chisel3 (#1572)
  • Add documentation of new plugin. (#1573)
  • Fix load memory from file to work with binary (#1583)
  • Improved speed of ChiselPlugin (#1590)
  • Support using switch without importing SwitchContext (#1595)
  • Added website docs and mdoc. (#1560)
    Added living documentation with repository. This will enable us to enforce better documentation of new features as part of their upstream process.

Miscellany

The removal of unstable methods from chisel3.core from the public API has been delayed. They will be removed with the version 3.4.0 release.

  • README: add link to website source. Now easier to figure out how to help enhance the content (#1420)(#1570)
  • Updated PR template to include checklist and documentation updates (#1562)
  • Update sbt-site to 1.4.0 (#1395)
  • Update scalacheck-1-14 to 3.1.1.1 (#1413)
  • Update sbt to 1.3.10 (#1415)
  • Update Mergify rules to backport to 3.3.x (#1429)
  • Update scalatest 3.1.2 (#1430)
  • verilator_4_016 --> v4.016 (#1459)
  • Restore backporting to 3.2.x (#1460)
  • Have defaultVersions specify complete ModuleIDs. (#1479)
  • Fix Mergify Backport labeling for 3.2.x (#1489)
  • Don't run FIRRTL in FlattenSpec's ChiselStage (#1493)
  • Add .scala-steward.conf (#1495)
  • fix treadle dependency for mill (#1504)
  • Update Development Meetings Info (#1511)
  • Add Treadle to CI builds (#1516)
  • Update build instructions in README (#1524)
  • Instance API for Importing Modules (#1530)
  • Select: update to work with records, Instances work, next need to add plugin (#1525)
  • Update OneHot.scala (#1539)
  • Remove ChiselLegacyAnnotation It was private and unused (#1544)
  • Bump Scala to 2.12.12 (#1553)
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