Add Vivado XSim as a simulator #2363
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rachitnigam
reviewed
Nov 28, 2024
| @@ -329,7 +329,7 @@ fn emit_component<F: io::Write>( | |||
| if let Some(check) = | |||
| emit_guard_disjoint_check(dst, asgns, &pool, true) | |||
| { | |||
| writeln!(f, "always_comb begin")?; | |||
| writeln!(f, "always_ff @(posedge clk) begin")?; | |||
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Can you explain this change? On the face of it, it is turning combinational logic into sequential logic and I'm not sure why I would expect this to be correct?
rachitnigam
reviewed
Nov 28, 2024
| [-help|-h] | ||
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| Description: xxxxxxxxxxxxxxxxxxx. | ||
| xxxxxxxxxxxxxxxxxxx. |
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We should probably provide a helpful description for this script here.
rachitnigam
reviewed
Nov 28, 2024
| @@ -20,7 +20,7 @@ fn xilinx_setup(e) { | |||
| ); | |||
| e.arg("pool", "console"); // Lets Ninja stream the tool output "live." | |||
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| // Compile an `.xo` file to an `.xclbin` file, which is where the actual EDA work occurs. | |||
| // Compile an `.xo` ile to an `.xclbin` file, which is where the actual EDA work occurs. | |||
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Thanks for getting us started on this! Having support for XSim is definitely a big win and we should get this merged. Couple of questions for the code but broadly, could you explain why the changes are needed? |
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Adds vivado xsim as a choice of simulator to fud2 because I want to use some encrypted IPs that can't be simulated by Verilator. XSim is slower than verilator by a lot so little reason for others to use it unless they want to use Xilinx floating point IP. It also behaves differently on some verilog constructs, so I had to make some fixes there (these fixes should also help calyx generated verilog work better on all time based (as opposed to cycle based like verilator) simulators).
Not really sure how to update the fud2 test cases but I won't do that until people agree with the other changes anyways.