Verilog source code for the Novena High Speed Analog Front End.
Capture data at 1GSPS from ADC and buffer in DDR3 memory.
Perform burst reads of the data via EIM to the host CPU.
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High Speed Analog Front End FPGA Firmware for Novena PVT1
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c-x-r/novena-afe-hs-fpga
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High Speed Analog Front End FPGA Firmware for Novena PVT1
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- Verilog 100.0%