Merging 2.x branches tasks,emul,dbgr:

* add Mach-O loader and system.osx skeleton * modify emulator module to match dbgr api (wip) * add server and basic client cmdcli ui * fix various errors/warnings
bdcht · Mar 2, 2020 · e547ec8 · e547ec8
1 parent 42e4417
commit e547ec8
Show file tree

Hide file tree

Showing 53 changed files with 2,789 additions and 535 deletions.
diff --git a/README.rst b/README.rst
@@ -78,6 +78,13 @@ Please see `LICENSE`_.
 Changelog
 =========
 
+- `v2.9.1`_
+
+  * add Mach-O loader and system.osx skeleton
+  * improve emulator module
+  * add server and basic client cmdcli ui
+  * fix various errors/warnings
+
 - `v2.9.0`_
 
   * add skeleton of emulator module (emul class)
@@ -306,6 +313,7 @@ Changelog
 .. _ply: http://www.dabeaz.com/ply/
 .. _sqlalchemy: http://www.sqlalchemy.org
 .. _LICENSE: https://github.com/bdcht/amoco/blob/release/LICENSE
+.. _v2.9.1: https://github.com/bdcht/amoco/releases/tag/v2.9.1
 .. _v2.9.0: https://github.com/bdcht/amoco/releases/tag/v2.9.0
 .. _v2.6.3: https://github.com/bdcht/amoco/releases/tag/v2.6.3
 .. _v2.6.2: https://github.com/bdcht/amoco/releases/tag/v2.6.2

diff --git a/amoco/arch/arm/v7/asm.py b/amoco/arch/arm/v7/asm.py
@@ -116,7 +116,7 @@ def i_ADC(i,fmap):
     cond,dest,op1,op2 = __pre(i,fmap)
     result,cout,overflow = AddWithCarry(fmap(op1),fmap(op2),fmap(C))
     fmap[dest] = stst(cond,result,fmap(dest))
-    if dest is pc:
+    if dest == pc:
         __check_state(i,fmap)
     elif i.setflags:
         __setflags(fmap,cond,cout,result,overflow)
@@ -125,7 +125,7 @@ def i_ADD(i,fmap):
     cond,dest,op1,op2 = __pre(i,fmap)
     result,cout,overflow = AddWithCarry(fmap(op1),fmap(op2))
     fmap[dest] = stst(cond,result,fmap(dest))
-    if dest is pc:
+    if dest == pc:
         __check_state(i,fmap)
     elif i.setflags:
         __setflags(fmap,cond,cout,result,overflow)
@@ -303,7 +303,7 @@ def i_ROR(i,fmap):
     else:
         result,cout = ror(op1,op2), top(1)
     fmap[dest] = stst(cond,result,fmap(dest))
-    if dest is pc:
+    if dest == pc:
         __check_state(i,fmap)
     if i.setflags:
         __setflags(fmap,cond,cout,result)
@@ -472,15 +472,15 @@ def i_BFC(i,fmap):
     src  = fmap(dest)
     result = composer([src[0:lsb],cst(0,size),src[lsb+size:src.size]])
     fmap[dest] = stst(cond,result,fmap(dest))
-    if dest is pc:
+    if dest == pc:
         raise InstructionError(i)
 
 def i_BFI(i,fmap):
     cond,dest,src,lsb,size = __pre(i,fmap)
     src = fmap(src)
     result = composer([dest[0:lsb],src[lsb,lsb+size],dest[lsb+size:dest.size]])
     fmap[dest] = stst(cond,result,fmap(dest))
-    if dest is pc:
+    if dest == pc:
         raise InstructionError(i)
 
 def i_CLZ(i,fmap):

diff --git a/amoco/arch/arm/v7/formats.py b/amoco/arch/arm/v7/formats.py
@@ -26,7 +26,7 @@ def reglist(i,pos=-1):
 def deref(i,pos=-2):
     assert len(i.operands)>2
     base,offset = i.operands[pos], i.operands[pos+1]
-    if base is pc:
+    if base == pc:
         if i.address is not None: base = i.address
         if internals['isetstate']==0:
             base = base+8

diff --git a/amoco/arch/arm/v7/spec_thumb.py b/amoco/arch/arm/v7/spec_thumb.py
@@ -82,6 +82,7 @@ def A_default(obj,DN,Rm,Rdn):
 
 @ispec("16[ 1010 1 Rd(3) imm8(8) ]", mnemonic="ADD")
 def A_default(obj,Rd,imm8):
+  obj.setflags = False
   obj.d = env.regs[Rd]
   obj.n = env.sp
   obj.imm32 = env.cst(imm8<<2,32)
@@ -92,6 +93,7 @@ def A_default(obj,Rd,imm8):
 @ispec("16[ 1011 0000 0 imm7(7) ]", mnemonic="ADD")
 @ispec("16[ 1011 0000 1 imm7(7) ]", mnemonic="SUB")
 def A_default(obj,imm7):
+  obj.setflags = False
   obj.d = env.sp
   obj.n = env.sp
   obj.imm32 = env.cst(imm7<<2,32)
@@ -101,6 +103,7 @@ def A_default(obj,imm7):
 
 @ispec("16[ 01000100 DM 1101 Rdm(3) ]", mnemonic="ADD")
 def A_default(obj,DM,Rdm):
+  obj.setflags = False
   obj.d = env.regs[(DM<<3)+Rdm]
   obj.n = env.sp
   obj.m = obj.d
@@ -110,6 +113,7 @@ def A_default(obj,DM,Rdm):
 
 @ispec("16[ 01000100 1 Rm(4) 101 ]", mnemonic="ADD")
 def A_default(obj,Rm):
+  obj.setflags = False
   obj.d = env.sp
   obj.n = env.sp
   obj.m = env.regs[Rm]
@@ -119,6 +123,7 @@ def A_default(obj,Rm):
 
 @ispec("16[ 1010 0 Rd(3) imm8(8) ]", mnemonic="ADR", add=True)
 def A_adr(obj,Rd,imm8):
+  obj.setflags = False
   obj.d = env.regs[Rd]
   obj.imm32 = env.cst(imm8<<2,32)
   obj.operands = [obj.d,obj.imm32]
@@ -139,12 +144,14 @@ def A_default(obj,imm5,Rm,Rd):
 
 @ispec("16[ 1101 .cond(4) imm8(8) ]", mnemonic="B")
 def A_label(obj,imm8):
+  obj.setflags = False
   obj.imm32 = env.cst(imm8<<1,9).signextend(32)
   obj.operands = [obj.imm32]
   obj.type = type_control_flow
 
 @ispec("16[ 11100 imm11(11) ]", mnemonic="B")
 def A_label(obj,imm11):
+  obj.setflags = False
   obj.imm32 = env.cst(imm11<<1,12).signextend(32)
   obj.operands = [obj.imm32]
   obj.type = type_control_flow
@@ -153,6 +160,7 @@ def A_label(obj,imm11):
 @ispec("16[ 1101 1110 imm8(8) ]", mnemonic="BKPT")
 @ispec("16[ 1101 1111 imm8(8) ]", mnemonic="SVC")
 def A_default(obj,imm8):
+  obj.setflags = False
   obj.imm32 = env.cst(imm8,32)
   obj.operands = [obj.imm32]
   obj.type = type_cpu_state
@@ -161,6 +169,7 @@ def A_default(obj,imm8):
 @ispec("16[ 010001 11 0 Rm(4) 000 ]", mnemonic="BX")
 @ispec("16[ 010001 11 1 Rm(4) 000 ]", mnemonic="BLX")
 def A_default(obj,Rm):
+  obj.setflags = False
   obj.m = env.regs[Rm]
   if Rm==15 and obj.mnemonic=='BLX': raise InstructionError(obj)
   obj.operands = [obj.m]
@@ -170,6 +179,7 @@ def A_default(obj,Rm):
 @ispec("16[ 1011 0 0 #i 1 #imm5(5) Rn(3) ]", mnemonic="CBZ")
 @ispec("16[ 1011 1 0 #i 1 #imm5(5) Rn(3) ]", mnemonic="CBNZ")
 def A_default(obj,i,imm5,Rn):
+  obj.setflags = False
   obj.n = env.regs[Rn]
   obj.imm32 = env.cst(int(i+imm5+'0',2),32)
   obj.operands = [obj.n, obj.imm32]
@@ -180,6 +190,7 @@ def A_default(obj,i,imm5,Rn):
 @ispec("16[ 010000 1010 Rm(3) Rn(3) ]", mnemonic="CMP")
 @ispec("16[ 010000 1000 Rm(3) Rn(3) ]", mnemonic="TST")
 def A_default(obj,Rm,Rn):
+  obj.setflags = False
   obj.n = env.regs[Rn]
   obj.m = env.regs[Rm]
   obj.operands = [obj.n, obj.m]
@@ -189,6 +200,7 @@ def A_default(obj,Rm,Rn):
 
 @ispec("16[ 001 01 Rn(3) imm8(8) ]", mnemonic="CMP")
 def A_default(obj,Rn,imm8):
+  obj.setflags = False
   obj.n = env.regs[Rn]
   obj.imm32 = env.cst(imm8,32)
   obj.operands = [obj.n, obj.imm32]
@@ -198,6 +210,7 @@ def A_default(obj,Rn,imm8):
 
 @ispec("16[ 010001 01 N Rm(4) Rn(3) ]", mnemonic="CMP")
 def A_default(obj,N,Rm,Rn):
+  obj.setflags = False
   obj.n = env.regs[(N<<3)+Rn]
   obj.m = env.regs[Rm]
   obj.operands = [obj.n, obj.m]
@@ -207,11 +220,13 @@ def A_default(obj,N,Rm,Rn):
 
 @ispec("16[ 1011 1111 .firstcond(4) .mask(4) ]", mnemonic="IT")
 def A_default(obj):
+  obj.setflags = False
   obj.type = type_cpu_state
   obj.cond = env.CONDITION_AL
 
 @ispec("16[ 1100 1 Rn(3) ~register_list(8) ]", mnemonic="LDM")
 def A_reglist(obj,Rn,register_list):
+  obj.setflags = False
   obj.n = env.regs[Rn]
   obj.registers = [env.regs[i] for i,r in enumerate(register_list) if r==1]
   if len(obj.registers)<1: raise InstructionError(obj)
@@ -222,6 +237,7 @@ def A_reglist(obj,Rn,register_list):
 
 @ispec("16[ 1100 0 Rn(3) ~register_list(8) ]", mnemonic="STM")
 def A_reglist(obj,Rn,register_list):
+  obj.setflags = False
   obj.n = env.regs[Rn]
   obj.registers = [env.regs[i] for i,r in enumerate(register_list) if r==1]
   obj.wback = True
@@ -236,6 +252,7 @@ def A_reglist(obj,Rn,register_list):
 @ispec("16[ 100 0 0 imm5(5) Rn(3) Rt(3) ]", mnemonic="STRH",_s=1)
 @ispec("16[ 011 0 0 imm5(5) Rn(3) Rt(3) ]", mnemonic="STR", _s=2)
 def A_deref(obj,imm5,Rn,Rt,_s):
+  obj.setflags = False
   obj.n = env.regs[Rn]
   obj.t = env.regs[Rt]
   obj.imm32 = env.cst(imm5<<_s,32)
@@ -249,6 +266,7 @@ def A_deref(obj,imm5,Rn,Rt,_s):
 @ispec("16[ 1001 1 Rt(3) imm8(8) ]", mnemonic="LDR")
 @ispec("16[ 1001 0 Rt(3) imm8(8) ]", mnemonic="STR")
 def A_deref(obj,Rt,imm8):
+  obj.setflags = False
   obj.n = env.sp
   obj.t = env.regs[Rt]
   obj.imm32 = env.cst(imm8<<2,32)
@@ -261,6 +279,7 @@ def A_deref(obj,Rt,imm8):
 
 @ispec("16[ 01001 Rt(3) imm8(8) ]", mnemonic="LDR")
 def A_deref(obj,Rt,imm8):
+  obj.setflags = False
   obj.n = env.pc
   obj.t = env.regs[Rt]
   obj.imm32 = env.cst(imm8<<2,32)
@@ -280,6 +299,7 @@ def A_deref(obj,Rt,imm8):
 @ispec("16[ 0101 010 Rm(3) Rn(3) Rt(3) ]", mnemonic="STRB")
 @ispec("16[ 0101 001 Rm(3) Rn(3) Rt(3) ]", mnemonic="STRH")
 def A_deref(obj,Rm,Rn,Rt):
+  obj.setflags = False
   obj.n = env.regs[Rn]
   obj.t = env.regs[Rt]
   obj.m = env.regs[Rm]
@@ -349,11 +369,13 @@ def A_default(obj,Rm,Rd):
 @ispec("16[ 1011 1111 0011 0000 ]", mnemonic="WFI")
 @ispec("16[ 1011 1111 0001 0000 ]", mnemonic="YIELD")
 def A_default(obj):
+  obj.setflags = False
   obj.type = type_cpu_state
   obj.cond = env.CONDITION_AL
 
 @ispec("16[ 1011 1 10 #P #register_list(8) ]", mnemonic="POP")
 def A_reglist(obj,P,register_list):
+  obj.setflags = False
   obj.registers = [env.regs[i] for i,r in enumerate(register_list[::-1]+'0'*7+P) if r=='1']
   obj.operands = [obj.registers]
   obj.type = type_data_processing
@@ -362,6 +384,7 @@ def A_reglist(obj,P,register_list):
 
 @ispec("16[ 1011 0 10 #M #register_list(8) ]", mnemonic="PUSH")
 def A_reglist(obj,M,register_list):
+  obj.setflags = False
   obj.registers = [env.regs[i] for i,r in enumerate(register_list[::-1]+'0'*6+M+'0') if r=='1']
   obj.operands = [obj.registers]
   obj.type = type_data_processing
@@ -379,6 +402,7 @@ def A_default(obj,Rn,Rd):
 
 @ispec("16[ 1011 0110 010 1 E 000 ]", mnemonic="SETEND")
 def instr_SETEND(obj,E):
+  obj.setflags = False
   obj.set_bigend = (E==1)
   obj.operands = [obj.set_bigend]
   obj.type = type_cpu_state

diff --git a/amoco/arch/arm/v7/spec_thumb2.py b/amoco/arch/arm/v7/spec_thumb2.py
@@ -23,37 +23,52 @@
 @ispec("32[ 0 #imm3(3) Rd(4) #imm8(8) 11110 #i 0 0010 S Rn(4) ]", mnemonic="ORR")
 @ispec("32[ 0 #imm3(3) Rd(4) #imm8(8) 11110 #i 0 0011 S Rn(4) ]", mnemonic="ORN")
 @ispec("32[ 0 #imm3(3) Rd(4) #imm8(8) 11110 #i 0 0100 S Rn(4) ]", mnemonic="EOR")
-@ispec("32[ 0 #imm3(3) Rd(4) #imm8(8) 11110 #i 0 1000 S Rn(4) ]", mnemonic="ADD")
 @ispec("32[ 0 #imm3(3) Rd(4) #imm8(8) 11110 #i 0 1010 S Rn(4) ]", mnemonic="ADC")
 @ispec("32[ 0 #imm3(3) Rd(4) #imm8(8) 11110 #i 0 1011 S Rn(4) ]", mnemonic="SBC")
-@ispec("32[ 0 #imm3(3) Rd(4) #imm8(8) 11110 #i 0 1101 S Rn(4) ]", mnemonic="SUB")
 @ispec("32[ 0 #imm3(3) Rd(4) #imm8(8) 11110 #i 0 1110 S Rn(4) ]", mnemonic="RSB")
 def A_default(obj,i,S,Rn,imm3,Rd,imm8):
-  obj.setflags = (S==1)
-  obj.n = env.regs[Rn]
-  obj.d = env.regs[Rd]
-  if Rn==13 and obj.mnemonic in ('ADD','SUB'):
-      if Rn==15 and S==0:
-          raise InstructionError(obj)
-  elif (BadReg(Rd) or Rn==15):
-      raise InstructionError(obj)
-  obj.imm32 = ThumbExpandImm(i+imm3+imm8)
-  obj.operands = [obj.d,obj.n,obj.imm32]
-  obj.type = type_data_processing
-  obj.cond = env.CONDITION_AL
+    obj.setflags = (S==1)
+    obj.n = env.regs[Rn]
+    obj.d = env.regs[Rd]
+    if (BadReg(Rd) or Rn==15):
+        raise InstructionError(obj)
+    obj.imm32 = ThumbExpandImm(i+imm3+imm8)
+    obj.operands = [obj.d,obj.n,obj.imm32]
+    obj.type = type_data_processing
+    obj.cond = env.CONDITION_AL
+
+@ispec("32[ 0 #imm3(3) Rd(4) #imm8(8) 11110 #i 1 0000 1 Rn(4) ]", mnemonic="ADD")
+@ispec("32[ 0 #imm3(3) Rd(4) #imm8(8) 11110 #i 1 0101 1 Rn(4) ]", mnemonic="SUB")
+def A_default(obj,i,Rn,imm3,Rd,imm8):
+    obj.setflags = True
+    obj.n = env.regs[Rn]
+    obj.d = env.regs[Rd]
+    if (Rd==15) or (Rn==13):
+        raise InstructionError(obj)
+    obj.imm32 = ThumbExpandImm(i+imm3+imm8)
+    obj.operands = [obj.d,obj.n,obj.imm32]
+    if (Rd==13) or (Rn==15):
+        obj.type = type_unpredictable
+    else:
+        obj.type = type_data_processing
+    obj.cond = env.CONDITION_AL
 
 @ispec("32[ 0 #imm3(3) Rd(4) #imm8(8) 11110 #i 1 0000 0 Rn(4) ]", mnemonic="ADD")
 @ispec("32[ 0 #imm3(3) Rd(4) #imm8(8) 11110 #i 1 0101 0 Rn(4) ]", mnemonic="SUB")
 def A_default(obj,i,Rn,imm3,Rd,imm8):
-  obj.setflags = False
-  obj.n = env.regs[Rn]
-  obj.d = env.regs[Rd]
-  if Rd==15 : raise InstructionError(obj)
-  # note: i, imm3, imm8 are provided as "01..." strings
-  obj.imm32 = cst(int(i+imm3+imm8,2),32)
-  obj.operands = [obj.d,obj.n,obj.imm32]
-  obj.type = type_data_processing
-  obj.cond = env.CONDITION_AL
+    obj.setflags = False
+    if BadReg(Rn) : raise InstructionError(obj)
+    obj.n = env.regs[Rn]
+    obj.d = env.regs[Rd]
+    # TODO: manual says its a ZeroExtend here, but need to double check with gdb
+    # cause its looks weird...
+    obj.imm32 = cst(int(i+imm3+imm8,2),32)
+    obj.operands = [obj.d,obj.n,obj.imm32]
+    if BadReg(Rd):
+        obj.type = type_unpredictable
+    else:
+        obj.type = type_data_processing
+    obj.cond = env.CONDITION_AL
 
 @ispec("32[ 0 imm3(3) Rd(4) imm2(2) stype(2) Rm(4) 11101 01 0000 S Rn(4) ]", mnemonic="AND")
 @ispec("32[ 0 imm3(3) Rd(4) imm2(2) stype(2) Rm(4) 11101 01 0001 S Rn(4) ]", mnemonic="BIC")
@@ -454,7 +469,7 @@ def A_default(obj,S,Rd,Rm):
   obj.m = env.regs[Rm]
   obj.operands = [obj.d, obj.m]
   obj.type = type_data_processing
-  if obj.mnemonic=="MOV" and (obj.d is env.pc):
+  if obj.mnemonic=="MOV" and (obj.d == env.pc):
     obj.type = type_control_flow
   if obj.mnemonic=="RRX":
       if BadReg(Rd) or BadReg(Rm): raise InstructionError(obj)

diff --git a/amoco/arch/arm/v7/utils.py b/amoco/arch/arm/v7/utils.py
@@ -74,7 +74,8 @@ def Shift_C(x, stype, shift, carry_in):
     if   stype==0: return LSL_C(x,shift)
     elif stype==1: return LSR_C(x,shift)
     elif stype==2: return ASR_C(x,shift)
-    elif stype==3: return RRX_C(x,carry_in) if shift==0 else ROR_C(x,shift)
+    elif stype==3: return ROR_C(x,shift)
+    elif stype==4: return RRX_C(x,carry_in)
 
 # reg is an instance of reg expression, shift is an integer or reg.
 def DecodeShift(stype, reg, shift):

diff --git a/amoco/arch/arm/v8/asm64.py b/amoco/arch/arm/v8/asm64.py
@@ -268,7 +268,7 @@ def i_ERET(i,fmap):
 def i_EXTR(i,fmap):
     fmap[pc] = fmap[pc]+i.length
     dst, op1, op2, lsb = i.operands
-    concat = composer(fmap(op2),fmap(op1))
+    concat = composer([fmap(op2),fmap(op1)])
     result = concat[lsb:lsb+i.datasize]
     fmap[dst] = result
 
@@ -318,9 +318,9 @@ def i_STLR(i,fmap):
     if i.pair:
         if not i.excl: raise InstructionError(i)
         if internals['endianstate']==0:
-            data = composer(i.t,i.t2)
+            data = composer([i.t,i.t2])
         else:
-            data = composer(i.t2,i.t)
+            data = composer([i.t2,i.t])
     else:
         data = i.t
     if i.excl:

diff --git a/amoco/arch/arm/v8/formats.py b/amoco/arch/arm/v8/formats.py
@@ -85,7 +85,6 @@ def alias_AND(i):
     return m.ljust(12) + ', '.join(r)
 
 def alias_BFM(i):
-    m = mnemo(i)
     r = regs(i)
     if i.imms<i.immr:
         r[3] = str(i.immr+1)