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Merge pull request #297 from bashtage/fix-rangomgen-advance
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BUG: Correct advance on systems without int128
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bashtage authored Oct 7, 2021
2 parents b50e08e + dfc00cf commit 0d44256
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Showing 5 changed files with 28 additions and 7 deletions.
3 changes: 1 addition & 2 deletions randomgen/common.pyx
Original file line number Diff line number Diff line change
Expand Up @@ -50,9 +50,8 @@ cdef class BitGenerator:
if isinstance(seed, ISEED_SEQUENCES):
if mode == "legacy":
raise ValueError("seed is a SeedSequence instance but mode is "
"\"legacy\". Using a SeedSequence implies "
"\"legacy\". Using a SeedSequence requires "
"mode=\"sequence\".")
mode = "sequence"
elif mode is None and seed is not None:
mode="sequence"
self.mode = mode.lower() if mode is not None else "sequence"
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3 changes: 1 addition & 2 deletions randomgen/src/pcg64/pcg64-common.c
Original file line number Diff line number Diff line change
Expand Up @@ -29,8 +29,7 @@ pcg128_t pcg_advance_lcg_128(pcg128_t state, pcg128_t delta, pcg128_t cur_mult,
}
cur_plus = pcg128_mult(pcg128_add(cur_mult, PCG_128BIT_CONSTANT(0u, 1u)), cur_plus);
cur_mult = pcg128_mult(cur_mult, cur_mult);
delta.low >>= 1;
delta.low += delta.high & 1;
delta.low = (delta.low >> 1) | (delta.high << 63);
delta.high >>= 1;
}
return pcg128_add(pcg128_mult(acc_mult, state), acc_plus);
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3 changes: 1 addition & 2 deletions randomgen/src/pcg64/pcg64.c
Original file line number Diff line number Diff line change
Expand Up @@ -97,8 +97,7 @@ pcg128_t pcg_advance_lcg_128(pcg128_t state, pcg128_t delta, pcg128_t cur_mult,
}
cur_plus = pcg128_mult(pcg128_add(cur_mult, PCG_128BIT_CONSTANT(0u, 1u)), cur_plus);
cur_mult = pcg128_mult(cur_mult, cur_mult);
delta.low >>= 1;
delta.low += delta.high & 1;
delta.low = (delta.low >> 1) | (delta.high << 63);
delta.high >>= 1;
}
return pcg128_add(pcg128_mult(acc_mult, state), acc_plus);
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24 changes: 24 additions & 0 deletions randomgen/tests/test_direct.py
Original file line number Diff line number Diff line change
Expand Up @@ -802,6 +802,8 @@ def setup_class(cls):
(-2,),
(2 ** 129 + 1,),
]
cls.large_advance_initial = 141078743063826365544432622475512570578
cls.large_advance_final = 32639015182640331666105117402520879107

def setup_bitgenerator(self, seed, mode="legacy", inc: Optional[int] = 0):
return self.bit_generator(*seed, mode=mode, variant="xsl-rr", inc=inc) # type: ignore
Expand Down Expand Up @@ -861,6 +863,14 @@ def test_unknown_variant(self):
with pytest.raises(ValueError):
PCG64(0, variant=3)

def test_large_advance(self):
bg = self.setup_bitgenerator([0], inc=1)
state = bg.state["state"]
assert state["state"] == self.large_advance_initial
bg.advance(sum(2 ** i for i in range(96)))
state = bg.state["state"]
assert state["state"] == self.large_advance_final


class TestPhilox(Random123):
@classmethod
Expand Down Expand Up @@ -1354,6 +1364,8 @@ def setup_class(cls):
(None, -1),
(None, 2 ** 129 + 1),
]
cls.large_advance_initial = 645664597830827402
cls.large_advance_final = 3

def setup_bitgenerator(self, seed, mode="legacy", inc=0):
return self.bit_generator(*seed, mode=mode, inc=inc)
Expand Down Expand Up @@ -1948,10 +1960,20 @@ def setup_class(cls):
else:
cls.invalid_seed_values += [("apple",)]
cls.seed_sequence_only = True
cls.large_advance_initial = 262626489767919729675955844831248137855
cls.large_advance_final = 326675794918500479020985263602132957772

def setup_bitgenerator(self, seed, mode=None, inc=0):
return self.bit_generator(*seed, inc=inc)

def test_large_advance(self):
bg = self.setup_bitgenerator([0], inc=1)
state = bg.state["state"]
assert state["state"] == self.large_advance_initial
bg.advance(sum(2 ** i for i in range(96)))
state = bg.state["state"]
assert state["state"] == self.large_advance_final


class TestPCG64CMDXSM(TestPCG64DXSM):
@classmethod
Expand All @@ -1960,6 +1982,8 @@ def setup_class(cls):
cls.bit_generator = partial(PCG64, mode="sequence", variant="dxsm")
cls.data1 = cls._read_csv(join(pwd, "./data/pcg64-cm-dxsm-testset-1.csv"))
cls.data2 = cls._read_csv(join(pwd, "./data/pcg64-cm-dxsm-testset-2.csv"))
cls.large_advance_initial = 159934576226003702342121456273047082943
cls.large_advance_final = 43406923282132296644520456716700203596


class TestEFIIX64(TestLXM):
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2 changes: 1 addition & 1 deletion setup.cfg
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
[metadata]
description-file = README.md
description_file = README.md
license_file = LICENSE.md

[flake8]
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