This repository contains an out-of-order (OoO) processor implemented in SystemVerilog. The project uses CMake as the build system and Verilator for SystemVerilog simulation.
Before building and running the project, make sure you have the following dependencies installed:
- CMake (version 3.27 or higher)
- Verilator
- C++ compiler supporting C++17
ld.lld
: installable via apt on linux orbrew install llvm
on macOS. Not necessary if you are not compiling new programs and using existing ELF's in testcases.
To build the project, follow these steps:
- Clone the repository and init submodules:
git clone <repository_url>
cd ooo_foxtrot
git submodule update --init --recursive
- Create a build directory and navigate to it:
mkdir build
cd build
- Run CMake to generate the build files:
cmake ..
- Build the project:
cmake --build .
This will compile the SystemVerilog sources and generate the executable files for the testbenches.
After building the project, you can run the testbenches:
- To run the example testbench:
./Vexample
- To run the cpu testbench:
./Vcpu ../testcases/example
The testbenches will simulate the respective SystemVerilog modules and display the simulation results.
To add a new testbench to the project, follow these steps:
- Create a new C++ testbench file in the
testbenches
directory, for example,testbenches/new_testbench.cpp
. - In the
CMakeLists.txt
file, add the following lines to define the new testbench executable and its corresponding SystemVerilog sources. Add any additional.cpp
files to theadd_executable
function that are needed to compile the executable, if necessary ( e.g.testbenches/support/memory.cpp
). You may not need to have${SV_WRAPPERS}
inSOURCES
if you don't need a wrapper:
add_executable(Vnew_testbench testbenches/new_testbench.cpp)
verilate(Vnew_testbench PREFIX Vnew_testbench SOURCES ${SV_SOURCES} ${SV_WRAPPERS} TOP_MODULE new_module INCLUDE_DIRS .)
- Save the
CMakeLists.txt
file. - Rebuild the project by running
cmake --build .
in the build directory.
./Vnew_testbench
Testcases are available in testcases/
directory with an additional README.md
for their format. They can be passed
into the Vcpu
testbench to load and run the CPU.