Skip to content

gateware/dsp: generic build/simulation logic, add upsampling in nco #9

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 5 commits into from
Jun 9, 2024
Merged
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension


Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
16 changes: 6 additions & 10 deletions .github/workflows/main.yml
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@ name: build & test
on: [push]

jobs:
ubuntu-example-usb-audio:
ubuntu-usb-audio:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v4
Expand All @@ -13,14 +13,14 @@ jobs:
- run: yosys --version
- run: |
pdm install
pdm build_example_usb_audio
pdm build_usb_audio
working-directory: gateware
- uses: actions/upload-artifact@v3
with:
name: example-usb-audio.bit
path: gateware/build/top.bit

ubuntu-example-dsp-svf:
ubuntu-bitstream-dsp-nco:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v4
Expand All @@ -30,14 +30,14 @@ jobs:
- run: yosys --version
- run: |
pdm install
pdm build_example_svf
pdm build_dsp_core nco
working-directory: gateware
- uses: actions/upload-artifact@v3
with:
name: example-dsp-svf.bit
path: gateware/build/top.bit

ubuntu-example-dsp-vca:
ubuntu-sim-dsp-nco:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v4
Expand All @@ -47,9 +47,5 @@ jobs:
- run: yosys --version
- run: |
pdm install
pdm build_example_vca
pdm sim_dsp_core nco
working-directory: gateware
- uses: actions/upload-artifact@v3
with:
name: example-dsp-vca.bit
path: gateware/build/top.bit
3 changes: 2 additions & 1 deletion gateware/.gitignore
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
# VCD traces
# waveform traces
*.fst
*.vcd

# Byte-compiled / optimized / DLL files
Expand Down
14 changes: 3 additions & 11 deletions gateware/pyproject.toml
Original file line number Diff line number Diff line change
Expand Up @@ -17,14 +17,6 @@ test = [

[tool.pdm.scripts]
test = { cmd = "pytest" }
build_example_usb_audio = { call = "example_usb_audio.top:build()" }
build_example_mirror = { call = "example_dsp.top:build_mirror()" }
build_example_svf = { call = "example_dsp.top:build_svf()" }
build_example_vca = { call = "example_dsp.top:build_vca()" }
build_example_delay = { call = "example_dsp.top:build_delay()" }
build_example_pitch = { call = "example_dsp.top:build_pitch()" }
build_example_matrix = { call = "example_dsp.top:build_matrix()" }
build_example_diffuser = { call = "example_dsp.top:build_diffuser()" }
build_example_waveshaper = { call = "example_dsp.top:build_waveshaper()" }
build_example_touchmix = { call = "example_dsp.top:build_touchmix()" }
build_example_nco = { call = "example_dsp.top:build_nco()" }
build_usb_audio = { call = "example_usb_audio.top:build()" }
build_dsp_core = { call = "example_dsp.top:build(sys.argv[1])" }
sim_dsp_core = { call = "example_dsp.top:simulate(sys.argv[1])" }
83 changes: 83 additions & 0 deletions gateware/src/example_dsp/sim_dsp_core.cpp
Original file line number Diff line number Diff line change
@@ -0,0 +1,83 @@
#if defined VM_TRACE_FST && VM_TRACE_FST == 1
#include <verilated_fst_c.h>
#endif

#include "Vcore.h"
#include "verilated.h"

#include <cmath>

int main(int argc, char** argv) {

VerilatedContext* contextp = new VerilatedContext;
contextp->commandArgs(argc, argv);
Vcore* top = new Vcore{contextp};

#if defined VM_TRACE_FST && VM_TRACE_FST == 1
Verilated::traceEverOn(true);
VerilatedFstC* tfp = new VerilatedFstC;
top->trace(tfp, 99); // Trace 99 levels of hierarchy (or see below)
tfp->open("simx.fst");
#endif
uint64_t sim_time = 100000000000;

contextp->timeInc(1);
top->rst = 1;
top->audio_rst = 1;
top->eval();

#if defined VM_TRACE_FST && VM_TRACE_FST == 1
tfp->dump(contextp->time());
#endif

contextp->timeInc(1);
top->rst = 0;
top->audio_rst = 0;
top->eval();

#if defined VM_TRACE_FST && VM_TRACE_FST == 1
tfp->dump(contextp->time());
#endif

uint32_t clkdiv = 0;
uint32_t n_clk_audio = 0;
uint32_t n_samples = 0;

while (contextp->time() < sim_time && !contextp->gotFinish()) {
// clk_sync ~= 60MHz
top->clk = !top->clk;
// clk_audio ~= 12MHz
if (clkdiv % 5 == 0) {
top->audio_clk = !top->audio_clk;
if (top->audio_clk) {
if (n_clk_audio % 256 == 0) {
top->fs_strobe = 1;
/*
top->pmod0_sample_i0 = (int16_t)20000.0*sin((float)pmod_clocks / 2000.0);
top->pmod0_sample_i1 = (int16_t)20000.0*cos((float)pmod_clocks / 50.0);
*/
//top->__024signal = 1000;
top->__024signal = (int16_t)10000.0*sin((float)n_samples / 50.0);
top->__024signal__0241 = (int16_t)10000.0*cos((float)n_samples / 10.0);
++n_samples;
} else {
if (top->fs_strobe) {
top->fs_strobe = 0;
}
}
++n_clk_audio;
}
}
contextp->timeInc(8333);
top->eval();
#if defined VM_TRACE_FST && VM_TRACE_FST == 1
tfp->dump(contextp->time());
#endif
clkdiv += 1;
}

#if defined VM_TRACE_FST && VM_TRACE_FST == 1
tfp->close();
#endif
return 0;
}
Loading
Loading