Weighted, pipelined, parameterized, parallelized priority encoding multiplexer

(VHDL-2008 only)

Given an array of inputs, it will choose the highest quality input

For multiple inputs with the same quality, it will choose the lowest numbered input

Quality is defined as the largest number for a subset of the input data field.

• For example the inputs can be a 32 bit number (set by the WIDTH parameter), and the quality can be the first N downto 0 bits of the input, where N is set by QLT_BITS

To do unweighted sorting (e.g. based on a valid bit only), just set QLT_BITS to 1 and make the valid bit the LSB of the data word

Both the data itself as well as the address of the data are output from the module

Inputs can be registered by setting REG_INPUT => true

Outputs can be registered by setting REG_OUTPUT => true

Enabling re-timing is recommended to best balance the flip-flops across stages.

Priority encoding happens in parallel, so the latency of the encoder scales as log2(N)

An illustrative example:

Pipeline registers can be inserted throughout the priority encoder tree with by setting REG_STAGES

• Setting REG_STAGES=0 will not insert any pipeline registers
• Setting REG_STAGES=N will insert pipeline registers on every Nth stage of the sorting tree

For example, on a tree with depth 8 (e.g. 256 bit wide encoder with 256 ⟶ 128 ⟶ 64 ⟶ 32 ⟶ 16 ⟶ 8 ⟶ 4 ⟶ 2 ⟶ 1) and REG_INPUT=1 , REG_OUTPUT=1, REG_STAGES=3:

• You would have a flip-flop at stage 0
• You would have a flip-flop at stage 3
• You would have a flip-flop at stage 6
• You would have a flip-flop at stage 7

VHDL Instantiation Template

priority_encoder_inst : entity work.priority_encoder
  generic map (
    WIDTH      => WIDTH,
    REG_INPUT  => REG_INPUT,
    REG_OUTPUT => REG_OUTPUT,
    REG_STAGES => REG_STAGES,
    DAT_BITS   => DAT_BITS,
    QLT_BITS   => QLT_BITS,
    ADR_BITS_o => integer(ceil(log2(real(WIDTH))))
    )
  port map (
    clock => clock,
    dav_i => dav_i,
    dav_o => dav_o,
    dat_i => dat_i,
    dat_o => dat_o,
    adr_o => adr_o
    );

Generics:

Generic	Description
WIDTH	# of inputs to the encoder
DAT_BITS	# of total bits per input
QLT_BITS	# of bits to use for sorting (N-1 downto 0)
REG_STAGES	Add a flip-flop every nth pipeline stage
REG_INPUT	true to register inputs with flip-flops
REG_OUTPUT	true to register outputs with flip-flops

Ports:

Port	Description
clock	Clock input
dat_i	2d array of inputs, WIDTH * DAT_BITS
dat_o	Data of the “best” output
adr_o	Address of the “best” output
dav_i	Data valid input; not used internally but latency of dav_i to dav_o will be equal to the latency through the encoder
dav_o	Data valid output; pipelined copy of dav_i

Testing