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Update MCR ERFO settings
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@sihyung-maxim
sihyung-maxim committed Sep 26, 2024
1 parent fd2fff0 commit 0464793
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Showing 3 changed files with 30 additions and 30 deletions.
16 changes: 8 additions & 8 deletions Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd
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Expand Up @@ -6352,8 +6352,8 @@
<addressOffset>0x10</addressOffset>
<fields>
<field>
<name>CLKSEL_32K</name>
<description>32KHz Clock Select for the system.</description>
<name>CLKSEL</name>
<description>Clcok Select for the RTC, System, WUT, and Timer.</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
Expand All @@ -6363,26 +6363,26 @@
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INRO</name>
<name>INRO_DIV4</name>
<description>INRO as clock source.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>EXTCLK</name>
<name>RTC_IN_DIV8</name>
<description>P0.12 div 8 as clock source.</description>
<value>2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLK32K_EN</name>
<description>Enable the 32KHz peripheral clock.</description>
<name>ERTCO32K_EN</name>
<description>Enable the 32KHz ERTCO.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTC4K_EN</name>
<description>Enable the 4KHz RTC Clock.</description>
<name>ERTCO_EN</name>
<description>Enable the ERTCO.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
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28 changes: 14 additions & 14 deletions Libraries/CMSIS/Device/Maxim/MAX32657/Include/mcr_regs.h
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Original file line number Diff line number Diff line change
Expand Up @@ -129,20 +129,20 @@ typedef struct {
* @brief Control Register
* @{
*/
#define MXC_F_MCR_CTRL_CLKSEL_32K_POS 0 /**< CTRL_CLKSEL_32K Position */
#define MXC_F_MCR_CTRL_CLKSEL_32K ((uint32_t)(0x3UL << MXC_F_MCR_CTRL_CLKSEL_32K_POS)) /**< CTRL_CLKSEL_32K Mask */
#define MXC_V_MCR_CTRL_CLKSEL_32K_ERTCO ((uint32_t)0x0UL) /**< CTRL_CLKSEL_32K_ERTCO Value */
#define MXC_S_MCR_CTRL_CLKSEL_32K_ERTCO (MXC_V_MCR_CTRL_CLKSEL_32K_ERTCO << MXC_F_MCR_CTRL_CLKSEL_32K_POS) /**< CTRL_CLKSEL_32K_ERTCO Setting */
#define MXC_V_MCR_CTRL_CLKSEL_32K_INRO ((uint32_t)0x1UL) /**< CTRL_CLKSEL_32K_INRO Value */
#define MXC_S_MCR_CTRL_CLKSEL_32K_INRO (MXC_V_MCR_CTRL_CLKSEL_32K_INRO << MXC_F_MCR_CTRL_CLKSEL_32K_POS) /**< CTRL_CLKSEL_32K_INRO Setting */
#define MXC_V_MCR_CTRL_CLKSEL_32K_EXTCLK ((uint32_t)0x2UL) /**< CTRL_CLKSEL_32K_EXTCLK Value */
#define MXC_S_MCR_CTRL_CLKSEL_32K_EXTCLK (MXC_V_MCR_CTRL_CLKSEL_32K_EXTCLK << MXC_F_MCR_CTRL_CLKSEL_32K_POS) /**< CTRL_CLKSEL_32K_EXTCLK Setting */

#define MXC_F_MCR_CTRL_CLK32K_EN_POS 3 /**< CTRL_CLK32K_EN Position */
#define MXC_F_MCR_CTRL_CLK32K_EN ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_CLK32K_EN_POS)) /**< CTRL_CLK32K_EN Mask */

#define MXC_F_MCR_CTRL_RTC4K_EN_POS 5 /**< CTRL_RTC4K_EN Position */
#define MXC_F_MCR_CTRL_RTC4K_EN ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_RTC4K_EN_POS)) /**< CTRL_RTC4K_EN Mask */
#define MXC_F_MCR_CTRL_CLKSEL_POS 0 /**< CTRL_CLKSEL Position */
#define MXC_F_MCR_CTRL_CLKSEL ((uint32_t)(0x3UL << MXC_F_MCR_CTRL_CLKSEL_POS)) /**< CTRL_CLKSEL Mask */
#define MXC_V_MCR_CTRL_CLKSEL_ERTCO ((uint32_t)0x0UL) /**< CTRL_CLKSEL_ERTCO Value */
#define MXC_S_MCR_CTRL_CLKSEL_ERTCO (MXC_V_MCR_CTRL_CLKSEL_ERTCO << MXC_F_MCR_CTRL_CLKSEL_POS) /**< CTRL_CLKSEL_ERTCO Setting */
#define MXC_V_MCR_CTRL_CLKSEL_INRO_DIV4 ((uint32_t)0x1UL) /**< CTRL_CLKSEL_INRO_DIV4 Value */
#define MXC_S_MCR_CTRL_CLKSEL_INRO_DIV4 (MXC_V_MCR_CTRL_CLKSEL_INRO_DIV4 << MXC_F_MCR_CTRL_CLKSEL_POS) /**< CTRL_CLKSEL_INRO_DIV4 Setting */
#define MXC_V_MCR_CTRL_CLKSEL_RTC_IN_DIV8 ((uint32_t)0x2UL) /**< CTRL_CLKSEL_RTC_IN_DIV8 Value */
#define MXC_S_MCR_CTRL_CLKSEL_RTC_IN_DIV8 (MXC_V_MCR_CTRL_CLKSEL_RTC_IN_DIV8 << MXC_F_MCR_CTRL_CLKSEL_POS) /**< CTRL_CLKSEL_RTC_IN_DIV8 Setting */

#define MXC_F_MCR_CTRL_ERTCO32K_EN_POS 3 /**< CTRL_ERTCO32K_EN Position */
#define MXC_F_MCR_CTRL_ERTCO32K_EN ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_ERTCO32K_EN_POS)) /**< CTRL_ERTCO32K_EN Mask */

#define MXC_F_MCR_CTRL_ERTCO_EN_POS 5 /**< CTRL_ERTCO_EN Position */
#define MXC_F_MCR_CTRL_ERTCO_EN ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_ERTCO_EN_POS)) /**< CTRL_ERTCO_EN Mask */

/**@} end of group MCR_CTRL_Register */

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16 changes: 8 additions & 8 deletions Libraries/PeriphDrivers/Source/SYS/SVD/mcr_me30.svd
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Original file line number Diff line number Diff line change
Expand Up @@ -42,8 +42,8 @@
<addressOffset>0x10</addressOffset>
<fields>
<field>
<name>CLKSEL_32K</name>
<description>32KHz Clock Select for the system.</description>
<name>CLKSEL</name>
<description>Clcok Select for the RTC, System, WUT, and Timer.</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
Expand All @@ -53,26 +53,26 @@
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INRO</name>
<name>INRO_DIV4</name>
<description>INRO as clock source.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>EXTCLK</name>
<name>RTC_IN_DIV8</name>
<description>P0.12 div 8 as clock source.</description>
<value>2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLK32K_EN</name>
<description>Enable the 32KHz peripheral clock.</description>
<name>ERTCO32K_EN</name>
<description>Enable the 32KHz ERTCO.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTC4K_EN</name>
<description>Enable the 4KHz RTC Clock.</description>
<name>ERTCO_EN</name>
<description>Enable the ERTCO.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
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