>>>This project and its source codes are available for educational purposes and not for commercial uses unless agreed/permitted. The distribution of this software after modifications on educational grounds must be mentioned explicitly. Anyone using or distributing this project completely or partially for commercial use can and will be subjected to proper legal actions according to international or regional laws, rules and regulations<<<
This is verilog-based RISC-V 32-bit-instruction-set-integer architecture processor core with hazard prevention unit and one bit external interrupt support. The test instruction memory is added and whoever is going to use it can change instruction memory as fits his/her testing criteria.