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Upstream rendering and timing fixes #32

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Upstream rendering and timing fixes #32

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5 changes: 3 additions & 2 deletions rtl/pce/huc6260.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -247,10 +247,10 @@ begin
end process;

HSYNC_START_POS <= 32-1 when DOTCLOCK = "00" else
66-1 when DOTCLOCK = "01" else
18-1 when DOTCLOCK = "01" else
LINE_CLOCKS-1;
HSYNC_END_POS <= 32+464-1 when DOTCLOCK = "00" else
66+468-1 when DOTCLOCK = "01" else
18+468-1 when DOTCLOCK = "01" else
468-1;
process( CLK )
begin
Expand All @@ -260,6 +260,7 @@ begin
VSYNC_F <= '0';
VSYNC_R <= '0';
if H_CNT = HSYNC_START_POS then HSYNC_F <= '1'; end if;
if H_CNT = HSYNC_START_POS + 1 and DOTCLOCK = "01" then HSYNC_F <= '1'; end if;
if H_CNT = HSYNC_END_POS then HSYNC_R <= '1'; end if;
if V_CNT = END_LINE-1 and H_CNT = LINE_CLOCKS-1 then VSYNC_F <= '1'; end if;
if V_CNT = VS_LINES-1 and H_CNT = LINE_CLOCKS-1 then VSYNC_R <= '1'; end if;
Expand Down
21 changes: 15 additions & 6 deletions rtl/pce/huc6270.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -54,6 +54,7 @@ entity HUC6270 is
SPR_CGY_DBG : out std_logic_vector(1 downto 0);
SPR_HF_DBG : out std_logic;
SPR_VF_DBG : out std_logic;
HSW_END_POS_DBG : out unsigned(6 downto 0);
HDS_END_POS_DBG : out unsigned(6 downto 0);
HDISP_END_POS_DBG : out unsigned(6 downto 0);
HSW_DBG : out std_logic_vector(4 downto 0);
Expand Down Expand Up @@ -175,6 +176,7 @@ architecture rtl of HUC6270 is
signal VDS : std_logic_vector(7 downto 0);
signal VDW : std_logic_vector(8 downto 0);
signal VDE : std_logic_vector(7 downto 0);
signal RES7M : std_logic_vector(0 downto 0);
signal HDISP : std_logic;
signal VDISP : std_logic;

Expand Down Expand Up @@ -296,6 +298,7 @@ begin
HDS <= (others=>'0');
HDE <= (others=>'0');
CM <= '0';
RES7M <= "0";
elsif rising_edge(CLK) then

FETCH_CE <= not FETCH_CE;
Expand All @@ -313,7 +316,7 @@ begin
if DOT_CNT = 7 then
TILE_CNT <= TILE_CNT + 1;
end if;
if TILE_CNT = HDE_END_POS or HSYNC_F = '1' then
if (TILE_CNT = HDE_END_POS and DOT_CNT = 7) or HSYNC_F = '1' then
DOT_CNT <= (others=>'0');
TILE_CNT <= (others=>'0');

Expand All @@ -327,21 +330,26 @@ begin
HDS <= HSR_HDS;
HDW <= HDR_HDW;
HDE <= HDR_HDE;
RES7M <= "0";

CM <= MWR_CM;
end if;
end if;

if DCK_CE = '0' and HSYNC_F = '1' then
RES7M <= "1";
end if;
end if;
end process;

FDOT_CNT <= DOT_CNT when SP64 = '0' else FETCH_DOT;
SPR_CE <= DCK_CE when SP64 = '0' else FETCH_CE;
SPR_MAX <= 15 when SP64 = '0' else 63;

HSW_END_POS <= "00"&unsigned(HSW);
HDS_END_POS <= ("00"&unsigned(HSW)) + 1 + unsigned(HDS);
HSW_END_POS <= "00"&unsigned(HSW) + ("000000"&unsigned(RES7M));
HDS_END_POS <= ("00"&unsigned(HSW)) + ("000000"&unsigned(RES7M)) + 1 + unsigned(HDS);
HDISP_END_POS <= ("00"&unsigned(HSW)) + 1 + unsigned(HDS) + 1 + unsigned(HDW);
HDE_END_POS <= ("00"&unsigned(HSW)) + 1 + unsigned(HDS) + 1 + unsigned(HDW) + unsigned(HDE);
HDE_END_POS <= ("00"&unsigned(HSW)) + 1 + unsigned(HDS) + 1 + unsigned(HDW) + 1 + unsigned(HDE);

VSW_END_POS <= ("00000"&unsigned(VSW));
VDS_END_POS <= ("00000"&unsigned(VSW)) + 1 + ("00"&unsigned(VDS)) + 1;
Expand Down Expand Up @@ -385,7 +393,7 @@ begin
if TILE_CNT = HSW_END_POS and DOT_CNT = 7 then
DISP_CNT_INC <= '1';
end if;
if (TILE_CNT = HDE_END_POS and DOT_CNT = 7 and DISP_CNT_INC = '1') or DISP_BREAK = '1' then
if DISP_BREAK = '1' then--(TILE_CNT = HDE_END_POS and DOT_CNT = 7 and DISP_CNT_INC = '1') or
DISP_CNT <= DISP_CNT + 1;
DISP_CNT_INC <= '0';
if DISP_CNT = VSW_END_POS then
Expand Down Expand Up @@ -785,7 +793,7 @@ begin
elsif rising_edge(CLK) then
SPR_TILE_SAVE <= '0';
if DCK_CE = '1' then
if TILE_CNT = HDS_END_POS - 2 and DOT_CNT = 7 and DISP_CNT >= VDS_END_POS and DISP_CNT < VDISP_END_POS then
if TILE_CNT = HDS_END_POS and DOT_CNT = 3 and DISP_CNT >= VDS_END_POS and DISP_CNT < VDISP_END_POS then
SPR_EVAL <= '1';
SPR_EVAL_X <= (others=>'0');
SPR_EVAL_CNT <= (others=>'0');
Expand Down Expand Up @@ -1430,6 +1438,7 @@ begin
SPR_HF_DBG <= SPR.HF;
SPR_VF_DBG <= SPR.VF;

HSW_END_POS_DBG <= HSW_END_POS;
HDS_END_POS_DBG <= HDS_END_POS;
HDISP_END_POS_DBG <= HDISP_END_POS;
HSW_DBG <= HSW;
Expand Down