Verilog code that implements GCD finder for pair of numbers from a list, that after running the appropriate scripts like Genus, Innovus and Voltus, will finally get a full and properly chip design after all the necessary steps: synthesis, CTS, placement, route and signoff.
There is the Verilog Behavioral code (which is synthesizable and will be finally mapped to gates) , and the TestBench code for the GateLevel simulation of the code.