ProjectAris

🕹️ ProjectAris aims at implementing a single core, single thread and RV32I based CPU in Verilog.

BTW it's named after AL1S from BlueArchive™.

Checkpoints

• week 6 创建仓库

• week 8 完成电路设计

• week 10 完成 Instruction Fetch 部分代码（see here），尝试仿真运行

• week 12 各个 CPU 模块文件基本完成，完成 cpu.v 连线（see code here）

• week 14 Simulation 通过 gcd

• week 16 Simulation 通过除 tak，heart，pi 之外的所有样例 (see code here)

• week 18 FPGA 通过所有样例

Design

• ISA: RISC-V 32-bit Integer, Unprivileged (supported instruction list see here, official spec see here)

• Arch: Out-of-Order scheduling with speculation, using Tomasulo's algorithm

• Feature: Single core, single thread, single issue, single ALU, with L1-ICache, without L1-DCache, without L2-Caches, single port RAM, physics address only

• Module details

  • ICache: Direct mapping instruction cache. Cache Line Size 16B (contains 4 instructions), Cache Line Number 32, ICache Size 16*32=512B;

  • Branch Predictor: Maintain 2-bit saturating counters for local branch history;

  • Regfile: 32 32-bit registers for data, each companied by a renaming register;

  • RS: Reservation Station, 16 entries, handling all instructions except L/S ones;

  • SLB: Store/Load Buffer, 16 entries, handling L/S instructions;

  • ROB: Reorder Buffer, 32 entries, handling instruction commits;

  • CDB: Common Data Bus, in this implementation there are separate buses for load results and ALU calculation results;

  • Memctrl: Handling Memory R/W requsts from ICache and SLB.

Performance

[Platform] WSL1, Ubuntu 20.04.1 LTS in windows 10 21H2 on Lenovo® LEGION™ laptop, with 11th Gen Intel® Core™ i5-11400H @ 2.70GHz processor

[Device] BASYS3™ Xilinx™ ARTIX™-7 FPGA, programed by Vivado® ML Edition 2022.2

(check Basys-3-Master.xdc for detailed implementation constrain information)

---

Test result with 100MHz clock frequency:

array_test1	array_test2	basicopt1	bugarian	expr	gcd
0.015625s	0.015625s	0.015625s	1.234375s	0.015625s	0.015625s
hanoi	heart	looper	lvalue2	magic	manyargument
1.218750s	775.7656s	0.015625s	0.015625s	0.031250s	0.000000s
multiarray	pi	qsort	queens	statement_test	superloop
0.015625s	1.875000s	4.500000s	1.062500s	0.000000s	0.015625s
tak	testsleep	uartboom
0.062500s	8.609375s	0.750000s

Performance comparison among different clock frequencies:

	WNS	TNS	WHS	THS	pi.c	heart.c
80MHz	0.872ns	0.000ns	0.079ns	0.000ns	2.359375s	971.453125s
100MHz	-0.779ns	-50.13ns	0.049ns	0.000ns	1.875000s	775.765625s
120MHz	-2.421ns	-874.5ns	0.018ns	0.000ns	1.531250s	633.546875s

Dependencies

• riscv-toolchain: RISC-V C and C++ cross-compiler, generating RV32I assembly code
• serial: USB-serial adapters for WSL, creating a serial connection with FPGA board
• iStyle: Verilog formatter used in the early stage of this project
• Vivado®: Integrated development environment for FPGA device (v2022.2)

Testing & Usage

Following methods are suitable for (and perhaps only for) WSL1 in windows 10

Check here for more configuration or debugging guidance.

MakeFile under riscv/ is provided for running simulation/FPGA tests.

Simulation

1. Install and configure riscv-gnu-toolchain;

2. Modify the riscv_toolchain varibale in riscv/MakeFile, use the path to riscv-toolchain on the device;

3. Under path riscv/, run the following script (replace <sim_testcase> with [can be part of] the name of the testcase) to trigger simulation test:

   make test_sim name=<sim_testcase> 

FPGA

1. Install and configure serial;

2. Connect FPGA device to PC/Laptop with a USB cable;

3. Use Vivado® IDE to generate bitstream file and program the FPGA device;

4. Determine the USB port ID of FPGA in the Windows Device Manager, assume it's COM4, run the following scripts in terminal to setup the environment:

   export LD_LIBRARY_PATH="/tmp/usr/local/lib/:$LD_LIBRARY_PATH"
   sudo chmod 666 /dev/ttyS4

5. Under path riscv/, run the following script (replace <fpga_testcase> with [can be part of] the name of the testcase) to trigger FPGA test:

   make test_fpga name=<fpga_testcase>

6. FPGA device may need to be rebooted or reprogrammed if alerts like UART assertion failed are raised.

About🤞

This project serves as an assignment for the course (2022-2023-1)-CS2951-1 in SJTU.

Consult the assignment repository for more infomation.