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[SEM-503] UMBus Comm Issue #205

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merged 2 commits into from
Jan 23, 2025
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Description

For some unknown / forgotten reason, the UMBus Drive Enable pin is connected to the serial (uart1) RTS pin, which makes no sense at all.
During update from kernel 4.14 to 5.15, the new UART driver began to drive this pin even when the serial is not open with hw flow control, blocking the UMbus communication.
The solution is a change in the device tree to remove the control of the pad USART3_RXD (wired to the UMBus Drive Enable signal) from the UART1 peripheral and connects it to the GPIO5 peripheral. That pad is now a gpio-hog pin of GPIO5 set to HIGH level.

How has this been tested

It was tested in an S6 and S8. The UMBus communication worked fine, including for firmware update.

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For some unknown / forgotten reason, the UMBus Drive Enable pin was connected to the serial (uart1) RTS pin, which makes no sense at all.
During update from kernel 4.14 to 5.15, the new UART driver starts driving this pin even when the serial is not open with hw flow control, blocking the UMbus communication.
This commit changes the device tree to remove the control of the pad USART3_RXD (wired to the UMBus Drive Enable signal) from the UART1 peripheral and connects it to the GPIO5 peripheral. That pad is now a gpio-hog pin of GPIO5 set to HIGH level.
- Add pins GPIO12 and GPIO13 to conform to congatec stock device tree. It has no effect on our system tho.
@alexborro alexborro requested a review from bryanfoley January 23, 2025 13:07
@alexborro alexborro changed the base branch from master/imx8 to master/imx8_revB January 23, 2025 13:07
@alexborro alexborro merged commit de2c269 into master/imx8_revB Jan 23, 2025
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2 participants