RISC-V-5-stage-pipelined-in-verilog

RISC-V PIPELINED PROCESSOR IN VERILOG. The Project is done in Embedded system design course for design of 5- stage pipelined RISC-V processor in Verilog supporting all formats of 32IM of RISC-V ISA. Project files of Intel Quartus prime are given.

Note:The project is under construction and I am adding new features like Caches design,Floating point etc.Thank you

Name		Name	Last commit message	Last commit date
Latest commit History 6 Commits
db		db
incremental_db		incremental_db
output_files		output_files
simulation		simulation
ALU.v		ALU.v
ALU.v.bak		ALU.v.bak
Control_E.v		Control_E.v
Control_E.v.bak		Control_E.v.bak
EXT.v		EXT.v
EXT.v.bak		EXT.v.bak
HazardUnit.v		HazardUnit.v
HazardUnit.v.bak		HazardUnit.v.bak
PC.v		PC.v
PC.v.bak		PC.v.bak
README.md		README.md
Reg.v		Reg.v
Reg.v.bak		Reg.v.bak
RegP.v		RegP.v
RegP.v.bak		RegP.v.bak
Verilog5.v.bak		Verilog5.v.bak
Waveform.vwf		Waveform.vwf
c5_pin_model_dump.txt		c5_pin_model_dump.txt
defination.v		defination.v
defination.v.bak		defination.v.bak
imemrom.txt		imemrom.txt
insmem.txt		insmem.txt
memfile.txt		memfile.txt
mux4.v		mux4.v
ram.v		ram.v
ram.v.bak		ram.v.bak
regfile.v		regfile.v
regfile.v.bak		regfile.v.bak
riscv_top.qpf		riscv_top.qpf
riscv_top.qsf		riscv_top.qsf
riscv_top.qws		riscv_top.qws
riscv_top.v		riscv_top.v
riscv_top.v.bak		riscv_top.v.bak
riscv_top_nativelink_simulation.rpt		riscv_top_nativelink_simulation.rpt
riscvtest.v		riscvtest.v
riscvtest.v.bak		riscvtest.v.bak
rom.v		rom.v
rom.v.bak		rom.v.bak

TheLeopardsH/RISC-V-5-stage-pipelined-in-verilog

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