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1. LF-Building-a-RISC-V-CPU-Core LF-Building-a-RISC-V-CPU-Core Public

   Forked from stevehoover/LF-Building-a-RISC-V-CPU-Core

   TL-Verilog 1

2. Binary-Phase-Shit-Keying-using-OpAmps-and-BJTs-on-LTSpice Binary-Phase-Shit-Keying-using-OpAmps-and-BJTs-on-LTSpice Public

   1

3. i2C_Protocol_simulation i2C_Protocol_simulation Public

   Forked from conquerorcj26/i2C_Protocol_simulation

   The objective of this project is to design and simulate i2C protocol using Verilog in Xilinx Vivado.

   Verilog

4. picorv32 picorv32 Public

   Forked from VigneshKarthikV/Mini-Project-in-VLSI-Design-EC383-

   Repository for the RTL to GDSII flow run on Openlane for Mini Project in VLSI Design

   Verilog

5. RISC-V-CPU-CORE RISC-V-CPU-CORE Public

   contains code I executed while building a RISC-V CPU

   TL-Verilog 1

6. TL-V_Projects TL-V_Projects Public

   Forked from TL-X-org/TL-V_Projects

   An overview of TL-Verilog resources and projects