Introduction

This is a pure systemverilog/verilog Testbench for risc-v SoCs. Those SoCs can be be generated by chipyard.

In chipyard simulation, the DUTs(risc-v cores) is tethered, which means the DUT(cores) can not be boot from memory automaticly.

And in this testbench , we build a testbench for standalone DUT which means the core can bringup itself (has its own bootrom, loads programs itself, etc).

How to run

Prerequirements

Make sure you have RISC-V gcc toolchain installed. 
Make sure the EDA simulation tools(VCS) is installed.

1. generate hex file for bootrom

    cd ./bootrom; 
    make hex;

you can see a .hex  file is generated in this folder.

2. generate hex file for SRAM

    cd ./case; 
    make all;

you can see a .hex  file is generated in this folder.

3. run RTL simulation

    cd ./vsim; 
    make run;

you can see the the string "Hello RISC-V!" is printed on the terminal. And a .fsdb waveform is emmited in the folder.

Tips: for more commands just refer to the Makefiles.

Directory Introduction

./bootrom

bootrom assemble program  which will be loaded in the maskrom(Address:0x10000)

./case

CPU initial programs and user programs.
Most of the code is porting from sifive freedom platform. 

./src

RISC-V SoC RTL files. Those files is generated by chipyard from chisel. 

./svtb

SystemVerilog testbench files.

./vsim

Scripts for VCS Simulation. 

References

The following repo is referenced.

1. https://github.com/ucb-bar/chipyard

2. https://github.com/sifive/freedom

3. https://github.com/sifive/freedom-e-sdk

4. https://github.com/SI-RISCV/e200_opensource