Tests

Resultados de los TESTs

Test preliminares:

• Fichero: prelim.s: OK! (Tanto en simulador como en real)

ZEXDOC

Test completados:

• Simulación: 58/67 (Fallan 9)
• Z80 en FPGA: 62/67 (Fallan 5)

Información por test

Num	Nombre	Sim	Descripción	Ciclos	Z80 Real
01	adc16	OK	<adc,sbc> hl,<bc,de,hl,sp>	38.912	OK
02	add16	OK	add hl,<bc,de,hl,sp>	19,456	OK
03	add16x	OK	add ix,<bc,de,ix,sp>	19,456	OK
04	add16y	OK	add iy,<bc,de,iy,sp>	19,456	OK
05	alu8i	OK	aluop a,nn	28,672	OK
06	alu8r	OK	aluop a,<b,c,d,e,h,l,(hl),a>	753,664	OK
07	alu8rx	FAIL	aluop a,<ixh,ixl,iyh,iyl>	376,832	OK
08	alu8x	OK	aluop a,(<ix,iy>+1)	229,376	OK
09	bitx	OK	bit n,(<ix,iy>+1)	2048	OK
10	bitz80	OK	bit n,<b,c,d,e,h,l,(hl),a>	49,152	OK
11	cpd1	FAIL	cpd	6144	FAIL
12	cpi1	OK	cpi	6144	FAIL
13	daa	OK	<daa,cpl,scf,ccf>	65,536	FAIL
14	inca	OK	<inc,dec> a	3072	OK
15	incb	OK	<inc,dec> b	3072	OK
16	incbc	OK	<inc,dec> bc	1536	OK
17	incc	OK	<inc,dec> c	3072	OK
18	incd	OK	<inc,dec> d	3072	OK
19	incde	OK	<inc,dec> de	1536	OK
20	ince	OK	<inc,dec> e	3072	OK
21	inch	OK	<inc,dec> h	3072	OK
22	inchl	OK	<inc,dec> hl	1536	OK
23	incix	OK	<inc,dec> ix	1536	OK
24	inciy	OK	<inc,dec> iy	1536	OK
25	incl	OK	<inc,dec> l	3072	OK
26	incm	OK	<inc,dec> (hl)	3072	OK
27	incsp	OK	<inc,dec> sp	1536	OK
28	incx	OK	<inc,dec> (<ix,iy>+1)	6144	OK
29	incxh	FAIL	<inc,dec> ixh	3072	FAIL
30	incxl	FAIL	<inc,dec> ixl	3072	OK
31	incyh	FAIL	<inc,dec> iyh	3072	OK
32	incyl	FAIL	<inc,dec> iyl	3072	OK
33	ld161	OK	ld <bc,de>,(nnnn)	32	OK
34	ld162	OK	ld hl,(nnnn)	16	OK
35	ld163	OK	ld sp,(nnnn)	16	OK
36	ld164	OK	ld <ix,iy>,(nnnn)	32	OK
37	ld165	OK	ld (nnnn),<bc,de>	64	OK
38	ld166	OK	ld (nnnn),hl	16	OK
39	ld167	OK	ld (nnnn),sp	16	OK
40	ld168	OK	ld (nnnn),<ix,iy>	64	OK
41	ld16im	OK	ld <bc,de,hl,sp>,nnnn	64	OK
42	ld16ix	OK	ld <ix,iy>,nnnn	32	OK
43	ld8bd	OK	ld a,<(bc),(de)>	44	OK
44	ld8im	OK	ld <b,c,d,e,h,l,(hl),a>,nn	64	OK
45	ld8imx	OK	ld (<ix,iy>+1),nn	32	OK
46	ld8ix1	OK	ld <b,c,d,e>,(<ix,iy>+1)	512	OK
47	ld8ix2	OK	ld <h,l>,(<ix,iy>+1)	256	OK
48	ld8ix3	OK	ld a,(<ix,iy>+1)	128	OK
49	ld8ixy	FAIL	ld <ixh,ixl,iyh,iyl>,nn	32	OK
50	ld8rr	OK	ld <bcdehla>,<bcdehla>	3456	OK
51	ld8rrx	FAIL	ld <bcdexya>,<bcdexya>	6912	FAIL
52	lda	OK	ld a,(nnnn) / ld (nnnn),a	44	OK
53	ldd1	OK	ldd (1)	44	OK
54	ldd2	OK	ldd (2)	44	OK
55	ldi1	OK	ldi (1)	44	OK
56	ldi2	OK	ldi (2)	44	OK
57	neg	OK	neg	16,384	OK
58	rld	OK	<rrd,rld>	7168	OK
59	rot8080	OK	<rlca,rrca,rla,rra>	6144	OK
60	rotxy	FAIL	shf/rot (<ix,iy>+1)	416	OK
61	rotz80	OK	shf/rot <b,c,d,e,h,l,(hl),a>	6784	OK
62	srz80	OK	<set,res> n,<bcdehl(hl)a>	7936	OK
63	srzx	OK	<set,res> n,(<ix,iy>+1)	1792	OK
64	st8ix1	OK	ld (<ix,iy>+1),<b,c,d,e>	1024	OK
65	st8ix2	OK	ld (<ix,iy>+1),<h,l>	256	OK
66	st8ix3	OK	ld (<ix,iy>+1),a	64	OK
67	stabd	OK	ld (<ix,iy>+1),a	96	OK

Más detalles de los vectores de los test fallados:

• Test 7: Op-code trap at 036e: dd 84

; aluop a,<ixh,ixl,iyh,iyl> (376,832 cycles)
alu8rx:	db	0d7h		; flag mask
	tstr	<0ddh,084h>,0d6f7h,0c76eh,0accfh,02847h,022ddh,0c035h,0c5h,038h,0234bh
	tstr	<020h,039h>,0,0,0,0,0,0,0,-1,0		; (8,192 cycles)
	tstr	0,0ffh,0,0,0,-1,-1,0d7h,0,0		; (46 cycles)
	db	0a4h,002h,06dh,05ah			; expected crc
	tmsg	'aluop a,<ixh,ixl,iyh,iyl>'

• Test 11

; cpd<r> (1) (6144 cycles)
	cpd1:	db	0d7h		; flag mask
		tstr	<0edh,0a9h>,0c7b6h,072b4h,018f6h,msbt+17,08dbdh,1,0c0h,030h,094a3h
		tstr	<0,010h>,0,0,0,0,0,010,0,-1,0		; (1024 cycles)
		tstr	0,0,0,0,0,0,0,0d7h,0,0			; (6 cycles)
		db	0a8h,07eh,06ch,0fah			; expected crc
		tmsg	'cpd<r>'

• Test 12

; cpi<r> (1) (6144 cycles)
cpi1:	db	0d7h		; flag mask
	tstr	<0edh,0a1h>,04d48h,0af4ah,0906bh,msbt,04e71h,1,093h,06ah,0907ch
	tstr	<0,010h>,0,0,0,0,0,010,0,-1,0		; (1024 cycles)
	tstr	0,0,0,0,0,0,0,0d7h,0,0			; (6 cycles)
	db	006h,0deh,0b3h,056h			; expected crc
	tmsg	'cpi<r>'

• Test 13

; <daa,cpl,scf,ccf>
daa:	db	0d7h		; flag mask
	tstr	027h,02141h,009fah,01d60h,0a559h,08d5bh,09079h,004h,08eh,0299dh
	tstr	018h,0,0,0,0,0,0,0d7h,-1,0		; (65,536 cycles)
	tstr	0,0,0,0,0,0,0,0,0,0			; (1 cycle)
	db	09bh,04bh,0a6h,075h			; expected crc
	tmsg	'<daa,cpl,scf,ccf>'

• Test 29: Op-code trap at 0366: dd 25

; <inc,dec> ixh (3072 cycles)
incxh:	db	0d7h		; flag mask
	tstr	<0ddh,024h>,0b838h,0316ch,0c6d4h,03e01h,08358h,015b4h,081h,0deh,04259h
	tstr	<0,1>,0,0ff00h,0,0,0,0,0,0,0		; (512 cycles)
	tstr	0,0,0,0,0,0,0,0d7h,0,0			; (6 cycles)
	db	06fh,046h,036h,062h			; expected crc
	tmsg	'<inc,dec> ixh'

• Test 30: Op-code trap at 0366: dd 2d

; <inc,dec> ixl (3072 cycles)
incxl:	db	0d7h		; flag mask
	tstr	<0ddh,02ch>,04d14h,07460h,076d4h,006e7h,032a2h,0213ch,0d6h,0d7h,099a5h
	tstr	<0,1>,0,0ffh,0,0,0,0,0,0,0		; (512 cycles)
	tstr	0,0,0,0,0,0,0,0d7h,0,0			; (6 cycles)
	db	002h,07bh,0efh,02ch			; expected crc
	tmsg	'<inc,dec> ixl'

• Test 31: Op-code trap at 0366: dd 25

; <inc,dec> iyh (3072 cycles)
incyh:	db	0d7h		; flag mask
	tstr	<0ddh,024h>,02836h,09f6fh,09116h,061b9h,082cbh,0e219h,092h,073h,0a98ch
	tstr	<0,1>,0ff00h,0,0,0,0,0,0,0,0		; (512 cycles)
	tstr	0,0,0,0,0,0,0,0d7h,0,0			; (6 cycles)
	db	02dh,096h,06ch,0f3h			; expected crc
	tmsg	'<inc,dec> iyh'

• Test 32: Op-code trap at 0366: dd 2d

; <inc,dec> iyl (3072 cycles)
incyl:	db	0d7h		; flag mask
	tstr	<0ddh,02ch>,0d7c6h,062d5h,0a09eh,07039h,03e7eh,09f12h,090h,0d9h,0220fh
	tstr	<0,1>,0ffh,0,0,0,0,0,0,0,0		; (512 cycles)
	tstr	0,0,0,0,0,0,0,0d7h,0,0			; (6 cycles)
	db	0fbh,0cbh,0bah,095h			; expected crc
	tmsg	'<inc,dec> iyl'

• Test 49: Op-code trap at 0370: dd 26

; ld <ixh,ixl,iyh,iyl>,nn (32 cycles)
ld8ixy:	db	0d7h		; flag mask
	tstr	<0ddh,026h>,03c53h,04640h,0e179h,07711h,0c107h,01afah,081h,0adh,05d9bh
	tstr	<020h,8>,0,0,0,0,0,0,0,0,0		; (4 cycles)
	tstr	0,0,0,0,0,0,0,0,-1,0			; (8 cycles)
	db	024h,0e8h,082h,08bh			; expected crc
	tmsg	'ld <ixh,ixl,iyh,iyl>,nn'

• Test 51: Op-code trap at 036d: dd 40

; ld <b,c,d,e,ixy,a>,<b,c,d,e,ixy,a> (6912 cycles)
ld8rrx:	db	0d7h		; flag mask
	tstr	<0ddh,040h>,0bcc5h,msbt,msbt,msbt,02fc2h,098c0h,083h,01fh,03bcdh
	tstr	<020h,03fh>,0,0,0,0,0,0,0,0,0		; (128 cycles)
	tstr	0,0ffh,0,0,0,-1,-1,0d7h,-1,0		; (54 cycles)
	db	047h,08bh,0a3h,06bh			; expected crc
	tmsg	'ld <bcdexya>,<bcdexya>'

• Test 60: Error de CRC. Código 80

; shift/rotate (<ix,iy>+1) (416 cycles)
rotxy:	db	0d7h		; flag mask
	tstr	<0ddh,0cbh,1,6>,0ddafh,msbt-1,msbt-1,0ff3ch,0dbf6h,094f4h,082h,080h,061d9h
	tstr	<020h,0,0,038h>,0,0,0,0,0,0,080h,0,0	; (32 cycles)
	tstr	0,0ffh,0,0,0,0,0,057h,0,0		; (13 cycles)
	db	071h,03ah,0cdh,081h			; expected crc
	tmsg	'shf/rot (<ix,iy>+1)'