PROJECT NOT UNDER ACTIVE MANAGEMENT

This project will no longer be maintained by Intel.
Intel has ceased development and contributions including, but not limited to, maintenance, bug fixes, new releases, or updates, to this project.
Intel no longer accepts patches to this project.
If you have an ongoing need to use this project, are interested in independently developing it, or would like to maintain patches for the open source software community, please create your own fork of this project.

D5005 FPGA Development Directory

This is the OFS D5005 Stratix 10 FPGA development top-level directory.

Directories

Evaluation Scripts (eval_scripts)

• Contains resources to report and setup D5005 development environment.

External Tools (external)

• Contains the software repositories needed for OFS/OPAE development and integration.
• Lightweight virtual environment containing the required Python packages needed for this repo and its tools.

IP Subsystems (ipss)

• Contains the code and supporting files that define or set up the IP subsystems contained in the D5005 FPGA Interface Manager (FIM)

Licensing for Quartus (license)

• Contains the license setup software for the version of Quartus used for this distribution/release of the D5005 product.

OFS Common Content Directory (Link to top-level directory ofs-common)

• Contains the scripts, source code, and verification environment resources that are common to all of the repositories.
• This directory is referenced via a link within each of the FPGA-Specific repositories.

Simulation

• Contains the testbenches and supporting code for all of the unit test simulations.
  • Bus Functional Model code is contained here.
  • Scripts are included for automating a myriad of tasks.
  • All of the individual unit tests and their supporting code is also located here.

FPGA Interface Module (FIM) Source code (src)

• This directory contains all of the structural and behavioral code for the FIM.
• Also included are scripts for generating the AXI buses for module interconnect.
• Top-level RTL for synthesis is located in this directory.
• Accelerated Functional Unit (AFU) infrastructure code is contained in this directory.

FPGA Synthesis

• This directory contains all of the scripts, settings, and setup files for running synthesis on the FIM.

Verification (UVM) (verification)

• This directory contains all of the scripts, testbenches, and test cases for the supported UVM tests for the D5005 FIM.
• NOTE: UVM resources are currently not available in this release due to difficulties in open-sourcing some components. It is hoped that this will be included in future releases.