Discussions

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  idea: do VHDL-Verilog one file at a time

  enhancement New feature or request help wanted Extra attention is needed

  suarezvictor started Mar 10, 2022 in General

  

  

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  How to support HDL style generics/parameterized types+functions, etc?

  enhancement New feature or request help wanted Extra attention is needed

  JulianKemmerer started Oct 2, 2021 in General

  

  

  3
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  Fake part with Fake timings

  enhancement New feature or request

  bartokon started Nov 9, 2021 in Ideas

  

  

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  Run PipelineC only once for given pipeline stages.

  bartokon started Nov 5, 2021 in Ideas

  

  

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  optimized leading zero counter

  suarezvictor started Oct 26, 2021 in Show and tell

  

  

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  Arithmetic cores

  suarezvictor started Oct 1, 2021 in Ideas

  

  

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  working fp32 multiplier using 8x8 multipliers

  suarezvictor started Oct 24, 2021 in Show and tell

  

  

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  Run pipelineC in browser

  suarezvictor started Oct 15, 2021 in Ideas

  

  

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  Math library

  suarezvictor started Oct 1, 2021 in Show and tell

  

  

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  Graphical results

  suarezvictor started Oct 3, 2021 in Ideas

  

  

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  Ideas for getting (software) people into PipelineC+FPGAs

  JulianKemmerer started Oct 2, 2021 in Ideas

  

  

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  Automatic tests on simulator

  suarezvictor started Sep 30, 2021 in Ideas

  

  

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  Simulation with Verilator

  suarezvictor started Sep 28, 2021 in Show and tell

  

  

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  Compatibility with C

  suarezvictor asked Sep 16, 2021 in Q&A · Unanswered

  

  

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  Video simulator

  suarezvictor started Sep 30, 2021 in Show and tell

  

  

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  Achieved simulation of PipelineC with CXXRTL

  suarezvictor started Sep 17, 2021 in Show and tell

  

  

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  Pipeline depth calculation

  suarezvictor started Sep 27, 2021 in Ideas

  

  

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  Welcome to PipelineC Discussions!

  JulianKemmerer started Dec 8, 2020 in General

  

  

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