Enable bit-manipulation extensions to RISC-V

[OBarronCS]

In reference to #2539, this PR enables certain RISC-V ISA extensions in assembly passed to the asm function in pwntools. It simply adds the zba, zbb, zbc, and zbs extension strings to CLI arguments passed to the assembler.

There is a long list of other ISA extensions outlined in this doc - https://gcc.gnu.org/onlinedocs/gcc/RISC-V-Options.html, but these 4 were chosen purely because they are general purpose and I happened to have run into them (many of the other ones are related to increasing performance of cryptographic functions or are SIMD-related).

The original issue mentions the possibility of exposing more functionality in the asm() function to allow the user to have more control over the assembler/compile process. In this case, as mentioned by @Arusekk in #2539, this is not needed. Currently, examples of where this would be nice don't immediately come to mind.

[Arusekk]

Is gbc not enough? The full B extension seems safe to enable, as well as V I guess (no plain instruction should get sneakily converted to a vector instruction I guess).

[OBarronCS]

I'm unable to find any information referencing the use of b to enable the B extension. It outputs the following error:

Error: cannot find default versions of the ISA extension `b'

I think adding the v extension would work, and added it in the latest commit (and removed zbc which wasn't actually considered a B extension, see here riscv/riscv-b#5 (comment)). Although