Discussions

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  How to instanciate FABulous primitives?

  mtetrault asked Mar 6, 2026 in Q&A · Answered

  

  

  

  

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  Request for io_pin_order.yaml for FABulous tiles

  Guha37 asked Mar 12, 2026 in Q&A · Answered

  

  

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  Questions on Tile Placement and Configuration Memory Implementation in FABulous

  Guha37 asked Mar 5, 2026 in Q&A · Answered

  

  

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  Partial reconfiguration support.

  nathanchandanson asked Mar 2, 2026 in Q&A · Answered

  

  

  

  

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  CLB Tile with Different size LUTs

  ThVerg asked Jan 19, 2026 in Q&A · Unanswered

  

  

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  Is FABulator bugged?

  ThVerg asked Oct 17, 2025 in Q&A · Answered

  

  

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  Seeking Guidance on nextpnr Fmax Reporting and Fabric Timing Integration

  ketan170102030 asked Dec 9, 2025 in General · Unanswered

  

  

  

  

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  Error in simulation with 24*24 eFPGA

  ketan170102030 asked Oct 23, 2025 in Q&A · Answered

  

  

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  PnR completed but Bitstream generation failed

  ThVerg asked Oct 13, 2025 in Q&A · Answered

  

  

  

  

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  Not able to run simulation for custom tile due to BEL component instantiations difference

  ketan170102030 asked Sep 8, 2025 in Q&A · Answered

  

  

  

  

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  Error while generating switch matrix list for Custom tile CRC5

  ketan170102030 asked Aug 18, 2025 in General · Answered

  

  

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  Template BEL for FlipFlopChain ConfigBitMode

  AndreaMazzan asked May 30, 2025 in Q&A · Unanswered

  

  

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  Clarification on area allocation and architectural purpose of I/O interface tiles in eFPGA Design

  Guha37 asked Jun 19, 2025 in Q&A · Unanswered

  

  

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  Increasing the Bit Size of the LUT Tile/BEL?

  sj-0142 asked Jun 9, 2025 in Q&A · Unanswered

  

  

  

  

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  What is the biggest eFPGA that can be created using FABulous in terms of number of tiles?

  shankar59 asked May 30, 2025 in Q&A · Answered

  

  

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  Trouble with creation of a custom I- and O-Tile (one direction)

  yannickreiss asked May 30, 2025 in Q&A · Closed · Unanswered

  

  

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  Greyhound: a RISC-V SoC with tightly coupled eFPGA on IHP SG13G2

  mole99 asked Apr 7, 2025 in Show and tell · Unanswered

  

  

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  timing constraint for asic implementation of efpga fabric

  hnpatel81 asked Mar 19, 2025 in Q&A · Unanswered

  

  

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  Confusion in connecting ports in top_wrapper file for different user_designs (Solved)

  Guha37 asked Mar 5, 2025 in Q&A · Answered

  

  

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  Clarification on Bitstream Generation and FPGA Programming for Emulation

  Guha37 asked Feb 14, 2025 in Q&A · Unanswered

  

  

  

  

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  Bitstream Documentation

  KelvinChung2000 asked Feb 12, 2025 in Q&A · Unanswered

  

  

  

  

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  Semantic versioning and auto release

  KelvinChung2000 asked Feb 10, 2025 in General · Unanswered

  

  

  

  

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  multiple clock domains in FABulous

  hnpatel81 asked Feb 20, 2025 in Q&A · Unanswered

  

  

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  VHDL support for user code

  hnpatel81 asked Feb 20, 2025 in Q&A · Unanswered

  

  

  

  

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  module <IO_1_bidirectional_frame_config_pass>，its function is complete？

  iii11879 asked Feb 19, 2025 in Q&A · Unanswered

  

  

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