Releases: ClarkFieseln/FPGA_HW_SIM_FWK
Simulation rate improved from 100Hz to 250Hz
1.0.11:
#######
- improved real clock rate from max. 100Hz to max. 250Hz by avoiding:
- use of string += in scheduler
- use of event.wait() which shows a delay of approx. 10ms -> thus the limit of 100Hz
Now time.sleep() is used instead
See # for more information.
*** NOTE: a separate project using a slightly different approach shows clock rates of up to 25kHz !!! ***
*** A new separate project with improved transfer rates will be uploaded to GitHub soon. ***
- added current clock frequency at the center of the FPGA chip
- added workaround to avoid showing zero temperature (in reality we show the CPU load which results sometimes in a zero value)
discovered problems:
- set_spi_din_to_zero() takes too much time!
-> if we use Events(): big jitter, big delay (approx. 10ms)
-> if we use Locks(): miss incomming SPI_SCK while inside set_spi_din_to_zero()
-> if we use a queue(): everything is again delayed and not synchronized!
SPI needs its own scheduler, but this again could be problematic,
here again we need an overall Scheduler with TX, RX synched and asynch events simulated in between.
ADC example, read temperature over SPI
ADC (LTC2314-14) with SPI interface provides temperature readings which are then displayed (probe).
Bugs in settings and logging corrected
corrected bugs:
- mainWindow.on_leResetSecs_editingFinished(): reset_for_seconds now set with float value
- use of logging.basicConfig() now with parameter force=True so changes really take effect
- logging.info() for Pause, Resume, On, Off added
- added createTempFiles() to leds_fifo so mainWindow doesn't need to distinguish between fifo-based and shared-files-based LEDs when updating settings
Performance improvement
- *** performance improvement:
digital inputs, switches and buttons now set in separate threads in order to NOT wait until "slow file handling" is done before doing the next file handling to set the signals to zero or one.
Note: still, for some reason the "overall" performance improvement is not so big.
Added __thread_set_one/zero() and __set_one/zero(). - BUG corrected: call to self.clock.updateGuiDefs() added where missing # NOTE: self.CLOCK_PERIOD_SEC is set within this call
- BUG corrected: initialization of class variables now completely inside init()
- CLOCK_PERIOD_SEC removed as argument to some object creations as not needed (leds, digital_outputs)
- several small improvements
Generic/common VHDL modules
- several redundant modules in VHDL like hw_sim_fwk_buttons.vhd were removed.
Instead, these 2 new "common/generic" modules are used (*):
hw_sim_fwk_file_read.vhd
hw_sim_fwk_fifo_write.vhd
(similarly, in the python code there is still potential to create common base classes, e.g. for digital_outputs and leds_fifo) - add missing file:
hw_sim_fwk_pipe_common.vhd
(sorry!!! I guess this was missing in previous tags)
(*) NOTE: in the VHDL code we have:
file_read (python_app -> VHDL) e.g. buttons, switches, digital_inputs (common use of hw_sim_fwk_file_read.vhd)
file_write (VHDL -> python_app) *** no longer used as it has a bad performance *** (exception as option hw_sim_fwk_leds.vhd)
-----------------------------
fifo_read (python_app -> VHDL) only clock (option hw_sim_fwk_digital_inputs_fifo as exception with own implementation)
fifo_write (VHDL -> python_app) e.g. digital_outputs, leds (common use of hw_sim_fwk_fifo_write.vhd)
LEDs with FIFOs
- leds updated over FIFOs (previous implementation as shared files left as option)
- scheduler gets on creation a single reference to all needed objects i.o. list of individual objects
- widget variables renamed to x_wdg
Code refactored (mainWindow.py -> new modules)
code in mainWindow.py refactored to other new modules:
buttons, clock, digital_inputs, digital_outputs,leds, reset, scheduler, switches, etc.
Use of oclock.Event i.o. threading.Event
- use of oclock.Event() to cope with innacuracy of threading.Event().
- improved and corrected performance logging
Several minor improvements
- log on variables to measure performance (see # TEST) shown on close()
- resolution for time() increased (?)
- more understandable example with DIs (only sync counter)
- replace() i.o. rename() as it is platform independent
- avoid setting DIs when bit of counter not changed (bug)
- corresponding changes on VHDL-side for edge-detections
FIFOs and shared files in Windows
The current version, tested on Win11, makes use of shared files and named pipes for communication between python-app and VHDL-code (simulator).
Besides several small improvements were made and some bugs corrected.