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Pull requests: CTSRD-CHERI/qemu

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Pull requests list

Fix build failure due to int-conversion
#281 opened Jun 14, 2025 by Flowdalic Loading…
1
Morello instruction tracing nops
#257 opened Jul 8, 2024 by qwattash Loading…
1
Disassemble instructions using current CPU state
#256 opened Jun 18, 2024 by arichardson Loading…
hw/net: e1000e: Clear ICR on read when using non MSI-X interrupts
#246 opened Feb 16, 2024 by verdantmoss Loading…
1
Unbreak -icount mode for RISC-V.
#243 opened Dec 19, 2023 by qwattash • Draft
2
(bsd-user MTTCG branch) Linux build fixes for system mode
#239 opened Sep 8, 2023 by tmarkettos Loading…
@kwitaszczyk
3
CLoadTags: Try accessing the first and last capability-size chunk
#233 opened Aug 3, 2023 by arichardson Loading…
3
Add GICv3 and UARTs to the morello board
#229 opened Jul 27, 2023 by damaki Loading…
6
Remove obsolete definition of debug_counter_names
#216 opened Apr 5, 2023 by minglechen Loading…
Fix RISCV and CHERI soft-tlb non page-aligned
#214 opened Feb 15, 2023 by LawrenceEsswood • Draft
2
Add tracing for total instruction count
#206 opened Oct 7, 2022 by minglechen Loading…
1
[instr logging] Log the faulting instruction before fault side-effects
#204 opened Aug 11, 2022 by arichardson • Draft
10
CHERI-RISC-V: PTE_CW/CD bugfix
#201 opened Aug 10, 2022 by nwf Loading…
CHERI-RISC-V As-User instructions and plumbing
#193 opened Nov 8, 2021 by nwf Loading…
CHERI-RISC-V: slightly rearrange SLTI HINT decoder
#180 opened Oct 14, 2021 by nwf Loading…
6
Refactor the instruction tracing subsystem.
#168 opened Sep 22, 2021 by qwattash Loading…
7
Try to workaround https://github.com/CTSRD-CHERI/qemu/issues/165
#166 opened Sep 13, 2021 by arichardson Loading…
Basic multi-threaded capability tag implementation
#158 opened Jul 19, 2021 by LawrenceEsswood Loading…
15
Memory versioning implementation (do not merge)
#143 opened Apr 27, 2021 by rmn30 Loading…
1
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