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  • Beijing
  • 08:55 (UTC +08:00)

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@nscscc2019 @OpenXiangShan
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AugustusWillisWang/README.md

Hi there 👋

  • I am currently working on CPU micro‑architecture, mainly focus on the design of the load store unit (LSU)
  • Used to be the maintainer of XiangShan processor's load store unit (LSU)
  • Fan of Falcom 軌跡 Series and Genshin Impact 🌟

Pinned

  1. OpenXiangShan/XiangShan OpenXiangShan/XiangShan Public

    Open-source high-performance RISC-V processor

    Scala 4.4k 610

  2. OSCPU/NutShell OSCPU/NutShell Public

    RISC-V SoC designed by students in UCAS

    Scala 1.3k 233

  3. nscscc2019/MIRROR-SWAMP nscscc2019/MIRROR-SWAMP Public

    MIRROR_SWAMP is a MIPS processor capable of booting linux, and it is specially optimized for DDR3 memory access pattern.

    Verilog 6 2

  4. OpenXiangShan/difftest OpenXiangShan/difftest Public

    Co-simulation framework for Xiangshan

    C++ 95 56