CoreValidation: Adapt path changes for Cortex-M core

ARM-software · Dec 21, 2022 · a8b2f56 · a8b2f56
1 parent 58bccd6
commit a8b2f56
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Showing 7 changed files with 12 additions and 12 deletions.
diff --git a/.github/workflows/caller-corevalidation.yml b/.github/workflows/caller-corevalidation.yml
@@ -5,7 +5,7 @@ on:
   pull_request:
     paths:
       - .github/workflows/caller-corevalidation.yml
-      - CMSIS/Core/**/*
+      - CMSIS/Core_M/**/*
       - CMSIS/Core_A/**/*
       - CMSIS/CoreValidation/**/*
       - Device/ARM/**/*

diff --git a/.github/workflows/codeql-analysis.yml b/.github/workflows/codeql-analysis.yml
@@ -5,15 +5,15 @@ on:
   push:
     branches: [ develop ]
     paths:
-      - 'CMSIS/Core/**'
+      - 'CMSIS/Core_M/**'
       - 'CMSIS/Core_A/**'
       - 'CMSIS/CoreValidation/**'
       - 'Device/ARM/**'
   pull_request:
     branches: [ develop ]
     paths:
       - '.github/workflows/codeql-analysis.yml'
-      - 'CMSIS/Core/**'
+      - 'CMSIS/Core_M/**'
       - 'CMSIS/Core_A/**'
       - 'CMSIS/CoreValidation/**'
       - 'Device/ARM/**'

diff --git a/.github/workflows/fileheader.yml b/.github/workflows/fileheader.yml
@@ -4,7 +4,7 @@ on:
   pull_request:
     branches: [ develop ]
     paths:
-      - 'CMSIS/Core/**'
+      - 'CMSIS/Core_M/**'
       - 'CMSIS/Core_A/**'
       - 'CMSIS/RTOS2/Include/**'
       - 'CMSIS/RTOS2/Source/**'

diff --git a/ARM.CMSIS.pdsc b/ARM.CMSIS.pdsc
@@ -1667,11 +1667,11 @@ and 8-bit Java bytecodes in Jazelle state.
       <files>
         <!-- CPU independent -->
         <file category="doc"     name="CMSIS/Documentation/Core/html/index.html"/>
-        <file category="include" name="CMSIS/Core/Include/"/>
-        <file category="header"  name="CMSIS/Core/Include/tz_context.h" condition="TrustZone"/>
+        <file category="include" name="CMSIS/Core_M4/Include/"/>
+        <file category="header"  name="CMSIS/Core_M4/Include/tz_context.h" condition="TrustZone"/>
         <!-- Code template -->
-        <file category="sourceC" attr="template" condition="TZ Secure" name="CMSIS/Core/Template/ARMv8-M/main_s.c"     version="1.1.1" select="Secure mode 'main' module for ARMv8-M"/>
-        <file category="sourceC" attr="template" condition="TZ Secure" name="CMSIS/Core/Template/ARMv8-M/tz_context.c" version="1.1.1" select="RTOS Context Management (TrustZone for ARMv8-M)" />
+        <file category="sourceC" attr="template" condition="TZ Secure" name="CMSIS/Core_M4/Template/ARMv8-M/main_s.c"     version="1.1.1" select="Secure mode 'main' module for ARMv8-M"/>
+        <file category="sourceC" attr="template" condition="TZ Secure" name="CMSIS/Core_M4/Template/ARMv8-M/tz_context.c" version="1.1.1" select="RTOS Context Management (TrustZone for ARMv8-M)" />
       </files>
     </component>
 

diff --git a/CMSIS/CoreValidation/Project/avh.yml b/CMSIS/CoreValidation/Project/avh.yml
@@ -6,7 +6,7 @@ backend:
     instance-type: t2.micro
 upload:
   - ARM.CMSIS.pdsc
-  - CMSIS/Core/**/*
+  - CMSIS/Core_M/**/*
   - CMSIS/Core_A/**/*
   - CMSIS/CoreValidation/**/*
   - -:CMSIS/CoreValidation/Project/Core_Validation-*.zip

diff --git a/Jenkinsfile b/Jenkinsfile
@@ -37,7 +37,7 @@ patternDocker = [
 ]
 
 patternCoreM = [
-    '^CMSIS/Core/Include/.*',
+    '^CMSIS/Core_M/Include/.*',
     '^Device/ARM/ARMCM.*'
 ]
 

diff --git a/linter.py b/linter.py
@@ -188,8 +188,8 @@ def check_build(self):
   def check_corem(self):
     """CMSIS-Core(M) version"""
     v = self.cmsis_corem_component()
-    self.verify_version("CMSIS/DoxyGen/Core/core.dxy", v)
-    self.verify_version("CMSIS/DoxyGen/Core/src/Overview.txt", v)
+    self.verify_version("CMSIS/DoxyGen/Core_M/core.dxy", v)
+    self.verify_version("CMSIS/DoxyGen/Core_M/src/Overview.txt", v)
     self.verify_version("CMSIS/DoxyGen/General/src/introduction.txt", v, component="CMSIS-Core (Cortex-M)")
     self.verify_version(self._pack.location(), v, component="CMSIS-Core(M)")