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README.md

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# C TBA
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##Author
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[Harris Zhu]([email protected])
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## Purpose
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use this demo to show how to communicate with C realtime.
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## Keys
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### get config data from C
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### support any memory width

clkgen.sv

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//
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// Created by : Harris Zhu
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// Filename : clkgen.sv
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// Author : Harris Zhu
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// Created On : 2016-11-15 20:36
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// Last Modified :
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// Update Count : 2016-11-15 20:36
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// Tags :
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// Description :
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// Conclusion :
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//
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//=======================================================================
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module clkgen;
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reg clk0=0;
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reg clk1=0;
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reg clk2=0;
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always #1 clk0 = ~clk0;
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always #2 clk1 = ~clk1;
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always #3 clk2 = ~clk2;
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initial
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begin
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force hw_top.u_dut.clk0 = clk0;
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force hw_top.u_dut.clk1 = clk1;
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force hw_top.u_dut.clk2 = clk2;
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end
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endmodule
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config.txt

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0x0000ffff
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0x0000fff0
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0x0000ff00
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0x0000f000
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0x00000000

dut.f

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clkgen.sv
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dut.v
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hw_top.sv
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memBFM.sv
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dutmem0.v
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dutmem1.v
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dutmem2.v

dut.v

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//
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// Created by : Harris Zhu
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// Filename : dut.v
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// Author : Harris Zhu
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// Created On : 2016-11-15 20:38
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// Last Modified :
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// Update Count : 2016-11-15 20:38
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// Tags :
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// Description :
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// Conclusion :
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//
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//=======================================================================
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module dut;
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parameter DWIDTH0 = 32;
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parameter DWIDTH1 = 16;
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parameter DWIDTH2 = 64;
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parameter AWIDTH0 = 10;
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parameter AWIDTH1 = 14;
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parameter AWIDTH2 = 16;
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reg [AWIDTH0-1:0] addr0;
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reg [AWIDTH1-1:0] addr1;
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reg [AWIDTH2-1:0] addr2;
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wire [DWIDTH0-1:0] dout0;
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wire [DWIDTH1-1:0] dout1;
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wire [DWIDTH2-1:0] dout2;
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reg [DWIDTH0-1:0] din0;
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reg [DWIDTH1-1:0] din1;
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reg [DWIDTH2-1:0] din2;
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wire clk0;
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wire clk1;
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wire clk2;
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reg rstn=0;
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reg ce0=1;
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reg ce1=1;
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reg ce2=1;
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reg we0=0;
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reg we1=0;
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reg we2=0;
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reg [31:0] cnt0=0;
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reg [27:0] cnt1=0;
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reg [15:0] cnt2=0;
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dutmem0 #(DWIDTH0, AWIDTH0) u_mem0(clk0, rstn, ce0, we0, addr0, din0, dout0);
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dutmem1 #(DWIDTH1, AWIDTH1) u_mem1(clk1, rstn, ce1, we1, addr1, din1, dout1);
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dutmem2 #(DWIDTH2, AWIDTH2) u_mem2(clk2, rstn, ce2, we2, addr2, din2, dout2);
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initial
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begin
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#10;
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rstn=1;
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end
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always @(posedge clk0)
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begin
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cnt0 <= cnt0 + 1;
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if(cnt0 % 17 == 0)
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begin
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we0 <= 1;
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end else if(cnt0 % 33 == 0)
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begin
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we0 <= 0;
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end
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end
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always @(posedge clk1)
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begin
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cnt1 <= cnt1 + 1;
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if(cnt1 % 19 == 0)
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begin
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we1 <= 1;
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end else if(cnt1 % 37 == 0)
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begin
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we1 <= 0;
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end
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end
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always @(posedge clk2)
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begin
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cnt2 <= cnt2 + 1;
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if(cnt2 % 23 == 0)
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begin
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we2 <= 1;
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end else if(cnt2 % 47 == 0)
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begin
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we2 <= 0;
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end
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end
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endmodule

dutmem0.v

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//
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// Created by : Harris Zhu
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// Filename : dutmem0.v
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// Author : Harris Zhu
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// Created On : 2016-11-15 23:37
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// Last Modified :
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// Update Count : 2016-11-15 23:37
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// Tags :
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// Description :
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// Conclusion :
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//
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//=======================================================================
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module dutmem0(clk, rstn, ce, we, addr, din, dout);
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parameter DWIDTH = 32;
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parameter AWIDTH = 10;
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parameter DEPTH = (1<<AWIDTH);
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input clk, rstn;
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input ce, we;
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input [AWIDTH-1:0] addr;
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input [DWIDTH-1:0] din;
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output [DWIDTH-1:0] dout;
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reg [DWIDTH-1:0] do_r;
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reg [DWIDTH-1:0] mem [0:DEPTH-1];
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always @(posedge clk)
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begin
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if(ce && we)
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begin
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mem[addr] <= din;
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end
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end
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always @(posedge clk)
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begin
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if(ce && !we)
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begin
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do_r <= mem[addr];
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end
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end
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assign dout = do_r;
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endmodule

dutmem1.v

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//
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// Created by : Harris Zhu
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// Filename : dutmem0.v
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// Author : Harris Zhu
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// Created On : 2016-11-15 23:37
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// Last Modified :
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// Update Count : 2016-11-15 23:37
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// Tags :
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// Description :
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// Conclusion :
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//
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//=======================================================================
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module dutmem1(clk, rstn, ce, we, addr, din, dout);
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parameter DWIDTH = 32;
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parameter AWIDTH = 10;
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parameter DEPTH = (1<<AWIDTH);
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input clk, rstn;
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input ce, we;
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input [AWIDTH-1:0] addr;
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input [DWIDTH-1:0] din;
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output [DWIDTH-1:0] dout;
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reg [DWIDTH-1:0] do_r;
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reg [DWIDTH-1:0] mem [0:DEPTH-1];
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always @(posedge clk)
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begin
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if(ce && we)
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begin
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mem[addr] <= din;
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end
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end
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always @(posedge clk)
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begin
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if(ce && !we)
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begin
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do_r <= mem[addr];
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end
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end
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assign dout = do_r;
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endmodule

dutmem2.v

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//
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// Created by : Harris Zhu
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// Filename : dutmem0.v
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// Author : Harris Zhu
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// Created On : 2016-11-15 23:37
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// Last Modified :
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// Update Count : 2016-11-15 23:37
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// Tags :
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// Description :
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// Conclusion :
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//
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//=======================================================================
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module dutmem2(clk, rstn, ce, we, addr, din, dout);
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parameter DWIDTH = 32;
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parameter AWIDTH = 10;
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parameter DEPTH = (1<<AWIDTH);
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input clk, rstn;
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input ce, we;
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input [AWIDTH-1:0] addr;
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input [DWIDTH-1:0] din;
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output [DWIDTH-1:0] dout;
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reg [DWIDTH-1:0] do_r;
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reg [DWIDTH-1:0] mem [0:DEPTH-1];
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always @(posedge clk)
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begin
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if(ce && we)
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begin
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mem[addr] <= din;
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end
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end
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always @(posedge clk)
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begin
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if(ce && !we)
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begin
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do_r <= mem[addr];
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end
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end
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assign dout = do_r;
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endmodule

hw_top.sv

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//
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// Created by : Harris Zhu
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// Filename : hw_top.sv
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// Author : Harris Zhu
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// Created On : 2016-11-15 20:35
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// Last Modified :
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// Update Count : 2016-11-15 20:35
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// Tags :
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// Description :
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// Conclusion :
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//
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//=======================================================================
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module hw_top;
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memBFM u_membfm();
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dut u_dut();
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clkgen u_clkgen();
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endmodule

libdpi.c

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#include <stdio.h>
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#include <svdpi.h>
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void getMem(int addr, int* data);
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int getConfig(int * addrArray, char* addrLen) {
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FILE* fh;
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int a;
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int anum=0;
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fh = fopen("config.txt", "r");
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if(fh==NULL) {
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printf("cannot open file config.txt!\n");
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exit(1);
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}
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while((fscanf(fh, "%x", &a)==1) && (anum<=64)) {
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addrArray[anum] = a;
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anum++;
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}
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*addrLen = anum;
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fclose(fh);
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return anum;
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}
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void trekFunc0(int data) {
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int dataArray[2];
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getMem(0x0000ffff, dataArray);
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}
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void trekFunc1(int data) {
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int dataArray[2];
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getMem(0x0000fff0, dataArray);
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}
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void trekFunc2(int data) {
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int dataArray[2];
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getMem(0x0000ff00, dataArray);
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}
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void getMem(int addr, int* data) {
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switch (addr)
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{
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case 0x0000ffff:
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data[0] = 0;
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data[0] = 1;
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break;
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case 0x0000fff0:
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data[0] = 2;
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data[0] = 3;
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break;
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case 0x0000ff00:
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data[0] = 4;
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data[0] = 5;
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break;
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default:
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data[0] = 6;
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data[0] = 7;
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break;
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}
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}

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