diff --git a/Source/HBIOS/Config/RCZ80_ez512_std.asm b/Source/HBIOS/Config/RCZ80_ez512_std.asm
index 9eb0d74e..71b096f7 100644
--- a/Source/HBIOS/Config/RCZ80_ez512_std.asm
+++ b/Source/HBIOS/Config/RCZ80_ez512_std.asm
@@ -66,7 +66,6 @@ VDAEMU_SERKBD	.SET	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
 ;
 CTCENABLE	.SET	TRUE		; ENABLE ZILOG CTC SUPPORT
 CTCBASE		.SET	KIOBASE+$04	; CTC BASE I/O ADDRESS
-CTCTIMER	.SET	TRUE		; ENABLE CTC PERIODIC TIMER
 CTCOSC		.SET	1843200		; CTC CLOCK FREQUENCY
 ;
 DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
@@ -79,9 +78,7 @@ SIOCNT		.SET	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
 SIO0MODE	.SET	SIOMODE_STD	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.SET	KIOBASE+$08	; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.SET	CTCOSC		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO0ACTCC	.SET	0		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 SIO0BCLK	.SET	CTCOSC		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO0BCTCC	.SET	1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 ;
 TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
 TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
diff --git a/Source/HBIOS/Config/RCZ80_k80w_std.asm b/Source/HBIOS/Config/RCZ80_k80w_std.asm
index 6bc62764..0556f904 100644
--- a/Source/HBIOS/Config/RCZ80_k80w_std.asm
+++ b/Source/HBIOS/Config/RCZ80_k80w_std.asm
@@ -59,17 +59,15 @@ AUTOCON		.SET	FALSE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
 ;
 CTCENABLE	.SET	TRUE		; ENABLE ZILOG CTC SUPPORT
 CTCBASE		.SET	KIOBASE+$04	; CTC BASE I/O ADDRESS
-CTCTIMER	.SET	TRUE		; ENABLE CTC PERIODIC TIMER
+CTCOSC		.SET	1843200		; CTC CLOCK FREQUENCY
 ;
 ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
 ;
 SIOCNT		.SET	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
 SIO0MODE	.SET	SIOMODE_STD	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.SET	KIOBASE+$08	; SIO 0: REGISTERS BASE ADR
-SIO0ACLK	.SET	1843200		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO0ACTCC	.SET	0		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO0BCLK	.SET	1843200		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO0BCTCC	.SET	1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO0ACLK	.SET	CTCOSC		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0BCLK	.SET	CTCOSC		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 ;
 VRCENABLE	.SET	TRUE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 ;
diff --git a/Source/ver.inc b/Source/ver.inc
index 6548fe96..f1edd913 100644
--- a/Source/ver.inc
+++ b/Source/ver.inc
@@ -2,7 +2,7 @@
 #DEFINE	RMN	5
 #DEFINE	RUP	0
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"3.5.0-dev.102"
+#DEFINE BIOSVER	"3.5.0-dev.103"
 #define rmj	RMJ
 #define rmn	RMN
 #define rup	RUP
diff --git a/Source/ver.lib b/Source/ver.lib
index c60af165..64bea136 100644
--- a/Source/ver.lib
+++ b/Source/ver.lib
@@ -3,5 +3,5 @@ rmn	equ	5
 rup	equ	0
 rtp	equ	0
 biosver	macro
-	db	"3.5.0-dev.102"
+	db	"3.5.0-dev.103"
 	endm