From 163aa5231c7ee465aadd260cacc61912416aeb97 Mon Sep 17 00:00:00 2001
From: Abhishek <abhishekdtu6@gmail.com>
Date: Mon, 12 Aug 2019 19:01:41 +0530
Subject: [PATCH 1/3] Extending the solutions to problems in Counter Section

---
 .../2 - Counters/5 - Four-digit Counter.v     |  36 +++++
 .../2 - Counters/6 - Twelve-Hour Clock.v      | 132 ++++++++++++++++++
 2 files changed, 168 insertions(+)
 create mode 100644 7 - Sequential Logic/2 - Counters/5 - Four-digit Counter.v
 create mode 100644 7 - Sequential Logic/2 - Counters/6 - Twelve-Hour Clock.v

diff --git a/7 - Sequential Logic/2 - Counters/5 - Four-digit Counter.v b/7 - Sequential Logic/2 - Counters/5 - Four-digit Counter.v
new file mode 100644
index 0000000..5b8b86f
--- /dev/null
+++ b/7 - Sequential Logic/2 - Counters/5 - Four-digit Counter.v	
@@ -0,0 +1,36 @@
+module top_module (
+    input clk,
+    input reset,   // Synchronous active-high reset
+    output [3:1] ena,
+    output [15:0] q);
+    
+    assign ena[1] = (q[3:0] == 9) ? 1 : 0;
+    assign ena[2] = ((q[7:4] == 9) && ena[1]) ? 1 : 0;
+    assign ena[3] = ((q[11:8] == 9) && ena[2]) ? 1 : 0;
+    
+    count_bcd c0(clk,reset,1,q[3:0]);
+    count_bcd c1(clk,reset,ena[1],q[7:4]);
+    count_bcd c2(clk,reset,ena[2],q[11:8]);
+    count_bcd c3(clk,reset,ena[3],q[15:12]);
+
+endmodule
+
+module count_bcd (
+    input clk,
+    input reset,        // Synchronous active-high reset
+    input ena,
+    output [3:0] q);
+
+    always@(posedge clk)
+        begin
+            if(reset)
+            	q <= 0;
+            else if (ena)
+            	if(q == 9)
+            		q <= 0;
+           		else
+                q <= q + 1;
+            else
+                q <= q;
+        end    	
+endmodule
diff --git a/7 - Sequential Logic/2 - Counters/6 - Twelve-Hour Clock.v b/7 - Sequential Logic/2 - Counters/6 - Twelve-Hour Clock.v
new file mode 100644
index 0000000..8745e0b
--- /dev/null
+++ b/7 - Sequential Logic/2 - Counters/6 - Twelve-Hour Clock.v	
@@ -0,0 +1,132 @@
+module top_module(
+    input clk,
+    input reset,
+    input ena,
+    output pm,
+    output [7:0] hh,
+    output [7:0] mm,
+    output [7:0] ss); 
+   
+    initial pm = 0;
+    
+    //counters for seconds
+    count_ss_L c_ss_l(clk,reset,ena,ss[3:0]);
+    count_ss_H c_ss_h(clk,reset,((ss[3:0] == 9) && ena),ss[7:4]);
+    
+    //counters for minutes
+    count_ss_L c_mm_l(clk,reset,(ena && (ss[3:0] == 9) && (ss[7:4] == 5)),mm[3:0]);
+    count_ss_H c_mm_h(clk,reset,(ena && (mm[3:0] == 9) && (ss[3:0] == 9) && (ss[7:4] == 5)),mm[7:4]);
+    
+    //counters for hours
+    count_hh_L c_hh_l(clk,reset,(ena && (mm[3:0] == 9) && (mm[7:4] == 5) && (ss[7:4] == 5) && (ss[3:0] == 9)),(hh[7:4]==1),pm,pm,hh[3:0]);
+    count_hh_H c_hh_h(clk,reset,(ena && ((hh[3:0] == 9) || ((hh[7:4] == 1) && (hh[3:0] == 2))) && (mm[3:0] == 9) && (mm[7:4] == 5) 
+																																															&& (ss[3:0]==9) && (ss[7:4] == 5)),hh[7:4]);
+   
+endmodule
+
+module count_hh_L (
+    input clk,
+    input reset,        // Synchronous active-high reset
+    input ena,
+    input incr_h,
+    input pm_curr,
+    output pm_new,
+    output [3:0] q);
+
+    always@(posedge clk)
+        begin
+            if(reset)
+             	begin
+             		q <= 2;
+                pm_new <= 0;
+             	end
+            else if (ena)
+            	begin
+              	if((q == 1) && incr_h)
+                	begin
+                  	 pm_new <= ~ pm_curr;                        
+                     q <= q + 1;
+                  end
+                 else if((q == 2) && incr_h)
+                 	begin
+                  	q <= 1;
+                    pm_new <= pm_curr;
+                  end
+                 else if(q == 9)
+                 	begin
+  						 			q <= 0;
+                    pm_new <= pm_curr;
+                  end
+           			 else
+                 	begin
+               			q <= q + 1;
+                    pm_new <= pm_curr;
+                  end
+                end
+            else
+            	begin
+              	q <= q;
+               	pm_new <= pm_curr;
+              end
+        	end    	
+endmodule
+
+module count_hh_H (
+    input clk,
+    input reset,        // Synchronous active-high reset
+    input ena,
+    output [3:0] q);
+
+    always@(posedge clk)
+        begin
+            if(reset)
+           	 q <= 1;
+            else if (ena)
+            	if(q == 1)
+              	q <= 0;
+              else
+              	q <= q + 1;
+            else
+           	 q <= q;
+        end    	
+endmodule
+
+module count_ss_L (
+    input clk,
+    input reset,        // Synchronous active-high reset
+    input ena,
+    output [3:0] q);
+
+    always@(posedge clk)
+        begin
+        	if(reset)
+          	q <= 0;
+          else if (ena)
+          	if(q == 9)
+            	q <= 0;
+           	else
+              q <= q + 1;
+          else
+          	q <= q;
+        end    	
+endmodule
+
+module count_ss_H (
+    input clk,
+    input reset,        // Synchronous active-high reset
+    input ena,
+    output [3:0] q);
+
+    always@(posedge clk)
+        begin
+        	if(reset)
+          	q <= 0;
+          	else if (ena)
+            	if(q == 5)
+            		q <= 0;
+           		else
+               	q <= q + 1;
+            else
+            	q <= q;
+        end    	
+endmodule

From 2a488bdbefe5e8deec36da33fd0db447e161ba84 Mon Sep 17 00:00:00 2001
From: Abhishek <abhishekdtu6@gmail.com>
Date: Wed, 14 Aug 2019 22:39:52 +0530
Subject: [PATCH 2/3] Added the solutions to Shift-Register problems

---
 .../1 - Four-bit Shift Register.v             | 26 +++++++++++
 .../2 - Left-Right Rotator.v                  | 28 ++++++++++++
 .../3 - Left-Right Arithmetic Shift.v         | 28 ++++++++++++
 .../3 - Shift Registers/4 - Five-Bit LFSR.v   | 33 ++++++++++++++
 .../3 - Shift Registers/5 - Three-Bit LFSR.v  | 22 ++++++++++
 .../6 - Thirty-Two-Bit LFSR.v                 | 28 ++++++++++++
 .../3 - Shift Registers/7 - Shift Register.v  | 21 +++++++++
 .../8 - Shift RegisterII.v                    | 34 ++++++++++++++
 .../3 - Shift Registers/9 - Three-Input LUT.v | 44 +++++++++++++++++++
 9 files changed, 264 insertions(+)
 create mode 100644 7 - Sequential Logic/3 - Shift Registers/1 - Four-bit Shift Register.v
 create mode 100644 7 - Sequential Logic/3 - Shift Registers/2 - Left-Right Rotator.v
 create mode 100644 7 - Sequential Logic/3 - Shift Registers/3 - Left-Right Arithmetic Shift.v
 create mode 100644 7 - Sequential Logic/3 - Shift Registers/4 - Five-Bit LFSR.v
 create mode 100644 7 - Sequential Logic/3 - Shift Registers/5 - Three-Bit LFSR.v
 create mode 100644 7 - Sequential Logic/3 - Shift Registers/6 - Thirty-Two-Bit LFSR.v
 create mode 100644 7 - Sequential Logic/3 - Shift Registers/7 - Shift Register.v
 create mode 100644 7 - Sequential Logic/3 - Shift Registers/8 - Shift RegisterII.v
 create mode 100644 7 - Sequential Logic/3 - Shift Registers/9 - Three-Input LUT.v

diff --git a/7 - Sequential Logic/3 - Shift Registers/1 - Four-bit Shift Register.v b/7 - Sequential Logic/3 - Shift Registers/1 - Four-bit Shift Register.v
new file mode 100644
index 0000000..7952ff0
--- /dev/null
+++ b/7 - Sequential Logic/3 - Shift Registers/1 - Four-bit Shift Register.v	
@@ -0,0 +1,26 @@
+module top_module(
+    input clk,
+    input areset,  // async active-high reset to zero
+    input load,
+    input ena,
+    input [3:0] data,
+    output reg [3:0] q); 
+
+    always @ (posedge clk or posedge areset)
+        begin
+        	if(areset)
+            	q <= 0;
+    		else if(load)
+                q <= data;
+            else if(ena)
+                begin
+                    q[0] = q[1];
+                    q[1] = q[2];
+                    q[2] = q[3];
+                    q[3] = 0;
+                end
+            else
+                q <= q;
+        end
+endmodule
+
diff --git a/7 - Sequential Logic/3 - Shift Registers/2 - Left-Right Rotator.v b/7 - Sequential Logic/3 - Shift Registers/2 - Left-Right Rotator.v
new file mode 100644
index 0000000..8e12f9a
--- /dev/null
+++ b/7 - Sequential Logic/3 - Shift Registers/2 - Left-Right Rotator.v	
@@ -0,0 +1,28 @@
+module top_module(
+    input clk,
+    input load,
+    input [1:0] ena,
+    input [99:0] data,
+    output reg [99:0] q); 
+    
+    integer i;
+    always@(posedge clk)
+        begin
+            if(load)
+                q <= data;
+            else if(ena == 1)
+                begin
+                    for(i = 0; i<100; i=i+1)
+                    		q[i] <= q[(i+1)%100];
+                end
+            else if(ena == 2)
+                begin
+                    for(i = 0; i<100;i=i+1)
+                        q[i] <= q[99 - (100-i)%100];
+                end
+            else
+                q <= q;
+        end
+
+endmodule
+
diff --git a/7 - Sequential Logic/3 - Shift Registers/3 - Left-Right Arithmetic Shift.v b/7 - Sequential Logic/3 - Shift Registers/3 - Left-Right Arithmetic Shift.v
new file mode 100644
index 0000000..f7f3021
--- /dev/null
+++ b/7 - Sequential Logic/3 - Shift Registers/3 - Left-Right Arithmetic Shift.v	
@@ -0,0 +1,28 @@
+module top_module(
+    input clk,
+    input load,
+    input ena,
+    input [1:0] amount,
+    input [63:0] data,
+    output reg [63:0] q); 
+    
+    always @ (posedge clk)
+        begin
+            if(load)
+                q <= data;
+            else if(ena)
+                begin
+                    if(amount == 0)
+                        q <= {q[62:0],1'b0};
+                    else if(amount == 1)
+                        q <= {q[55:0],8'b0};
+                    else if(amount == 2)
+                        q <= {{2{q[63]}},q[62:1]};
+            				else
+                        q <= {{9{q[63]}},q[62:8]};
+                end
+            else
+                q <= q;
+        end
+
+endmodule
diff --git a/7 - Sequential Logic/3 - Shift Registers/4 - Five-Bit LFSR.v b/7 - Sequential Logic/3 - Shift Registers/4 - Five-Bit LFSR.v
new file mode 100644
index 0000000..b205485
--- /dev/null
+++ b/7 - Sequential Logic/3 - Shift Registers/4 - Five-Bit LFSR.v	
@@ -0,0 +1,33 @@
+module top_module(
+    input clk,
+    input reset,    // Active-high synchronous reset to 5'h1
+    output [4:0] q
+); 
+    wire in1,in2,in3,in4,in5;
+    
+    assign in1 = reset ? 1'b1 : q[1];
+    assign in2 = reset ? 1'b0 : q[2];
+    assign in3 = reset ? 1'b0 : q[3] ^ q[0];
+    assign in4 = reset ? 1'b0 : q[4];
+    assign in5 = reset ? 1'b0 : q[0] ^ 1'b0;
+        
+    d_ff ff1(clk,in1,q[0]);
+    d_ff ff2(clk,in2,q[1]);
+    d_ff ff3(clk,in3,q[2]);
+    d_ff ff4(clk,in4,q[3]);
+    d_ff ff5(clk,in5,q[4]);
+
+endmodule
+
+module d_ff(
+input clk,
+    input d,
+    output q
+);
+    always @ (posedge clk)
+        begin
+            q <= d;
+        end
+endmodule
+
+
diff --git a/7 - Sequential Logic/3 - Shift Registers/5 - Three-Bit LFSR.v b/7 - Sequential Logic/3 - Shift Registers/5 - Three-Bit LFSR.v
new file mode 100644
index 0000000..54e897f
--- /dev/null
+++ b/7 - Sequential Logic/3 - Shift Registers/5 - Three-Bit LFSR.v	
@@ -0,0 +1,22 @@
+module top_module (
+input [2:0] SW,      // R
+input [1:0] KEY,     // L and clk
+output [2:0] LEDR);  // Q
+
+    reg [2:0] LEDR_Next;
+    
+    // NOTE: KEY[0] = CLK, KEY[1] = L;
+    always @(*)
+        begin
+            LEDR_Next[0] = KEY[1] ? SW[0] : LEDR[2];
+            LEDR_Next[1] = KEY[1] ? SW[1] : LEDR[0];
+            LEDR_Next[2] = KEY[1] ? SW[2] : LEDR[1] ^ LEDR[2];
+        end
+    
+    always @ (posedge KEY[0])
+        begin
+            LEDR <= LEDR_Next;
+        end
+
+endmodule
+
diff --git a/7 - Sequential Logic/3 - Shift Registers/6 - Thirty-Two-Bit LFSR.v b/7 - Sequential Logic/3 - Shift Registers/6 - Thirty-Two-Bit LFSR.v
new file mode 100644
index 0000000..d008c36
--- /dev/null
+++ b/7 - Sequential Logic/3 - Shift Registers/6 - Thirty-Two-Bit LFSR.v	
@@ -0,0 +1,28 @@
+module top_module(
+    input clk,
+    input reset,    // Active-high synchronous reset to 32'h1
+    output [31:0] q
+); 
+    reg [31:0] q_next;
+    
+    //NOTE: In a primitive shift register, the values are shifted by 1 every clock cycle. We make use of the same property here to define a combinational block feeding the values into the D-FF. The only change occurs in the value of inputs to the D-FF having taps
+    
+    always @ (*)
+        begin
+            q_next = q[31:1];
+            q_next[31] = q[0];
+            q_next[21] = q[22] ^ q[0];
+            q_next[1]  = q[2] ^ q[0];
+            q_next[0]  = q[1] ^ q[0];
+        end
+
+    always @ (posedge clk)
+        begin
+            if(reset)
+                q <= 32'b1;
+            else
+                q <= q_next;
+        end
+    
+endmodule
+
diff --git a/7 - Sequential Logic/3 - Shift Registers/7 - Shift Register.v b/7 - Sequential Logic/3 - Shift Registers/7 - Shift Register.v
new file mode 100644
index 0000000..2118ccb
--- /dev/null
+++ b/7 - Sequential Logic/3 - Shift Registers/7 - Shift Register.v	
@@ -0,0 +1,21 @@
+module top_module (
+    input clk,
+    input resetn,   // synchronous reset
+    input in,
+    output out);
+    
+    reg [3:0] outReg;
+    
+    always @ (posedge clk)
+        begin
+        if(~resetn)
+                outReg[3] <= 0;
+            else
+                begin
+                    outReg <= {in,outReg[2:0]};
+                end
+        end 
+    assign out = outReg[0];
+endmodule
+
+
diff --git a/7 - Sequential Logic/3 - Shift Registers/8 - Shift RegisterII.v b/7 - Sequential Logic/3 - Shift Registers/8 - Shift RegisterII.v
new file mode 100644
index 0000000..ce728ea
--- /dev/null
+++ b/7 - Sequential Logic/3 - Shift Registers/8 - Shift RegisterII.v	
@@ -0,0 +1,34 @@
+module top_module (
+    input [3:0] SW,
+    input [3:0] KEY,
+    output [3:0] LEDR
+); //
+    
+    // MUXDFF modn(clk,w,r,l,e,qin,qout)
+    MUXDFF mod1(KEY[0], LEDR[1], SW[0], KEY[2], KEY[1], LEDR[0], LEDR[0]);
+    MUXDFF mod2(KEY[0], LEDR[2], SW[1], KEY[2], KEY[1], LEDR[1], LEDR[1]);
+    MUXDFF mod3(KEY[0], LEDR[3], SW[2], KEY[2], KEY[1], LEDR[2], LEDR[2]);
+    MUXDFF mod4(KEY[0], KEY[3], SW[3], KEY[2], KEY[1], LEDR[3], LEDR[3]);
+
+endmodule
+
+module MUXDFF (
+    input clk,
+    input w,
+input r,
+input l,
+input e,
+    input qin,
+output qout);
+    
+    wire mux1Out,mux2Out;
+    
+    assign mux1Out = e ? w : qin;
+    assign mux2Out = l ? r: mux1Out;
+    
+    always @ (posedge clk)
+        qout <=mux2Out;
+
+endmodule
+
+
diff --git a/7 - Sequential Logic/3 - Shift Registers/9 - Three-Input LUT.v b/7 - Sequential Logic/3 - Shift Registers/9 - Three-Input LUT.v
new file mode 100644
index 0000000..7b964b5
--- /dev/null
+++ b/7 - Sequential Logic/3 - Shift Registers/9 - Three-Input LUT.v	
@@ -0,0 +1,44 @@
+module top_module (
+    input clk,
+    input enable,
+    input S,
+    input A, B, C,
+    output Z ); 
+
+    wire [7:0] qOut;
+    wire [2:0] sel;
+    assign sel = {A,B,C};
+    
+    d_ff mem(clk,enable,S,qOut);
+    
+    always @ (*)
+        begin
+            case(sel)
+                3'b000: Z = qOut[0];
+                3'b001: Z = qOut[1];
+                3'b010: Z = qOut[2];
+                3'b011: Z = qOut[3];
+                3'b100: Z = qOut[4];
+                3'b101: Z = qOut[5];
+                3'b110: Z = qOut[6];
+                3'b111: Z = qOut[7];
+            endcase
+        end
+endmodule
+
+module d_ff(
+    input clk,
+input en,
+input s,
+    output [7:0] q);
+    
+    always @ (posedge clk)
+        begin
+            if(en)
+                q <= {q[6:0],s};
+            else
+                q <= q;
+        end
+endmodule
+
+

From b0bd4ed2ea720337fec1ba2b407604d6adc09034 Mon Sep 17 00:00:00 2001
From: Abhishek <abhishekdtu6@gmail.com>
Date: Sun, 15 Sep 2019 19:06:54 +0530
Subject: [PATCH 3/3] Adding more solutions to More Circuits and FSM section

---
 .../4 - More Circuits/1 - Rule90.v            |  24 ++++
 .../4 - More Circuits/2 - Rule110.v           |  24 ++++
 .../1 - Simple FSM1 Synch.v                   |  76 ++++++++++++
 .../10 - Lemmings4.v                          |  89 ++++++++++++++
 .../11 - FsmOneHot.v                          |  25 ++++
 .../12 - PS2 Packet Parser.v                  |  35 ++++++
 .../13 - PS2 PAcket Parser DataPath.v         |  45 +++++++
 .../14 - Serial Receiver.v                    |  54 +++++++++
 .../15 - Serial Receiver DataPath.v           |  64 ++++++++++
 .../16 - Serial Receiver Parity Check.v.v     |  71 +++++++++++
 .../17 - Sequence Recognition.v               |  57 +++++++++
 .../18 - Mealey FSM.v                         |  58 +++++++++
 .../2 - Simple FSM1 Asynch.v                  |  30 +++++
 .../3 - Simple FSM2 Synch.v                   |  31 +++++
 .../4 - Simple State Transition3.v            |  31 +++++
 .../5 - Fsm3OneHot.v                          |  19 +++
 .../5 - Finite State Machines/6 - Moore FSM.v | 114 ++++++++++++++++++
 .../5 - Finite State Machines/7 - Lemmings1.v |  39 ++++++
 .../5 - Finite State Machines/8 - Lemmings2.v |  57 +++++++++
 .../5 - Finite State Machines/9 - Lemmings3.v |  72 +++++++++++
 20 files changed, 1015 insertions(+)
 create mode 100644 7 - Sequential Logic/4 - More Circuits/1 - Rule90.v
 create mode 100644 7 - Sequential Logic/4 - More Circuits/2 - Rule110.v
 create mode 100644 7 - Sequential Logic/5 - Finite State Machines/1 - Simple FSM1 Synch.v
 create mode 100644 7 - Sequential Logic/5 - Finite State Machines/10 - Lemmings4.v
 create mode 100644 7 - Sequential Logic/5 - Finite State Machines/11 - FsmOneHot.v
 create mode 100644 7 - Sequential Logic/5 - Finite State Machines/12 - PS2 Packet Parser.v
 create mode 100644 7 - Sequential Logic/5 - Finite State Machines/13 - PS2 PAcket Parser DataPath.v
 create mode 100644 7 - Sequential Logic/5 - Finite State Machines/14 - Serial Receiver.v
 create mode 100644 7 - Sequential Logic/5 - Finite State Machines/15 - Serial Receiver DataPath.v
 create mode 100644 7 - Sequential Logic/5 - Finite State Machines/16 - Serial Receiver Parity Check.v.v
 create mode 100644 7 - Sequential Logic/5 - Finite State Machines/17 - Sequence Recognition.v
 create mode 100644 7 - Sequential Logic/5 - Finite State Machines/18 - Mealey FSM.v
 create mode 100644 7 - Sequential Logic/5 - Finite State Machines/2 - Simple FSM1 Asynch.v
 create mode 100644 7 - Sequential Logic/5 - Finite State Machines/3 - Simple FSM2 Synch.v
 create mode 100644 7 - Sequential Logic/5 - Finite State Machines/4 - Simple State Transition3.v
 create mode 100644 7 - Sequential Logic/5 - Finite State Machines/5 - Fsm3OneHot.v
 create mode 100644 7 - Sequential Logic/5 - Finite State Machines/6 - Moore FSM.v
 create mode 100644 7 - Sequential Logic/5 - Finite State Machines/7 - Lemmings1.v
 create mode 100644 7 - Sequential Logic/5 - Finite State Machines/8 - Lemmings2.v
 create mode 100644 7 - Sequential Logic/5 - Finite State Machines/9 - Lemmings3.v

diff --git a/7 - Sequential Logic/4 - More Circuits/1 - Rule90.v b/7 - Sequential Logic/4 - More Circuits/1 - Rule90.v
new file mode 100644
index 0000000..9e5acf6
--- /dev/null
+++ b/7 - Sequential Logic/4 - More Circuits/1 - Rule90.v	
@@ -0,0 +1,24 @@
+module top_module(
+    input clk,
+    input load,
+    input [511:0] data,
+    output [511:0] q ); 
+    
+    integer i;
+    always @ (posedge clk)
+        begin
+            if(load)
+                q <= data;
+            else
+                for(i=0;i<512;i=i+1)
+                    begin
+                        if(i==0)
+                            q[i] <= 1'b0 ^ q[i+1];
+                        else if (i==511)
+                            q[i] <= q[i-1] ^ 1'b0;
+                        else
+                        q[i] <= q[i-1] ^ q[i+1];
+                    end
+        end
+
+endmodule
diff --git a/7 - Sequential Logic/4 - More Circuits/2 - Rule110.v b/7 - Sequential Logic/4 - More Circuits/2 - Rule110.v
new file mode 100644
index 0000000..255ca0a
--- /dev/null
+++ b/7 - Sequential Logic/4 - More Circuits/2 - Rule110.v	
@@ -0,0 +1,24 @@
+module top_module(
+    input clk,
+    input load,
+    input [511:0] data,
+    output [511:0] q
+); 
+ 	integer i;
+    always @ (posedge clk)
+        begin
+            if(load)
+                q <= data;
+            else
+                for(i=0;i<512;i=i+1)
+                    begin
+                        if(i==0)
+                            q[i] <= q[i];
+                        else if (i==511)
+                            q[i] <= (q[i] ^ q[i-1]) | (q[i-1] &q[i]) ;
+                        else
+                            q[i] <= (q[i] ^ q[i-1]) | (~q[i+1] & q[i] & q[i-1]);
+                    end
+        end
+endmodule
+
diff --git a/7 - Sequential Logic/5 - Finite State Machines/1 - Simple FSM1 Synch.v b/7 - Sequential Logic/5 - Finite State Machines/1 - Simple FSM1 Synch.v
new file mode 100644
index 0000000..b676459
--- /dev/null
+++ b/7 - Sequential Logic/5 - Finite State Machines/1 - Simple FSM1 Synch.v	
@@ -0,0 +1,76 @@
+// Note the Verilog-1995 module declaration syntax here:
+module top_module(clk, reset, in, out);
+    input clk;
+    input reset;    // Synchronous reset to state B
+    input in;
+    output out;//  
+    reg out;
+
+    // Fill in state name declarations
+
+    reg state;
+    //wire next_state;
+    parameter A= 1'b0,B= 1'b1;
+
+    //assign out = state ? 1 : 0;
+    
+    //combinational logic
+ always @ (state or in)
+   begin
+   	case(state)
+   		1'b0: if(in == 1) begin
+      				next_state <= A;
+   					end else
+     	 				next_state <= B;
+   		1'b1: if(in == 1)
+       				next_state <= B;
+   					else
+           		next_state <= A;
+   		default: next_state <= 1'b0;
+   endcase
+  end
+            
+  //Sequential logic
+	always @ (posedge clk)
+		begin
+    	if(reset) begin
+      	state <= B;
+      	out <= 1;
+    	end
+    	else
+        begin
+					case(state)
+						A: if(in) begin
+    						state <= A;
+              	out <= 0;
+							end else begin
+    						state <= B;
+                out <= 1;
+              end
+            B: if(in) begin
+    						state <= B;
+                out <= 1;
+               end  else begin
+        				state <= A;
+               	out <= 0;
+              end
+					default: state <= 1'b0;
+		 endcase
+ 		end
+	end
+            
+  //output logic
+  always @ (posedge clk)
+  	begin
+ 			if(reset)
+  			out <= 1'b1;
+  		else
+  			begin
+  				case(state)
+      			A: out <= 1'b0;
+      			B: out <= 1'b1;
+      			default: out <= 1'b0;
+  				endcase
+  			end
+  	end
+endmodule
diff --git a/7 - Sequential Logic/5 - Finite State Machines/10 - Lemmings4.v b/7 - Sequential Logic/5 - Finite State Machines/10 - Lemmings4.v
new file mode 100644
index 0000000..8c0c711
--- /dev/null
+++ b/7 - Sequential Logic/5 - Finite State Machines/10 - Lemmings4.v	
@@ -0,0 +1,89 @@
+module top_module(
+	input clk,
+    input areset,    // Freshly brainwashed Lemmings walk left.
+    input bump_left,
+    input bump_right,
+    input ground,
+    input dig,
+    output walk_left,
+    output walk_right,
+    output aaah,
+    output digging ); 
+
+    parameter WL = 0, WR = 1, DL = 2, DR = 3, FL = 4, FR = 5, SPL = 6;
+    reg [3:0] state, next_state;
+    int count;
+    
+    // State transition logic
+    always @ (*)
+        begin
+            case(state)
+                WL: if(~ground)
+                    	next_state = FL;
+               		else if(dig)
+                    	next_state = DL;
+                	else if(bump_left)
+                    	next_state = WR;
+                	else
+                   		next_state = state;
+                WR: if(~ground)
+                    	next_state = FR;
+                	else if(dig)
+                    	next_state = DR;
+                	else if(bump_right)
+                    	next_state = WL;
+                	else
+                    	next_state = state;
+                DL: if(~ground)
+                    	next_state = FL;
+                	else
+                    	next_state = state;
+                DR: if(~ground)
+                	    next_state = FR;
+                	else
+                    	next_state = state;
+                FL: if(ground)
+                        begin
+                            if(count > 19)
+                                next_state = SPL;
+                            else
+                   				next_state = WL;
+                        end
+                	else
+                    	next_state = state;
+                FR:if(ground)
+                        begin
+                            if(count > 19)
+                                next_state = SPL;
+                            else
+                    			next_state = WR;
+                        end
+                	else
+                    	next_state = state;
+                default: next_state = state;
+            endcase
+        end
+    
+    //Sequential logic
+    always @ (posedge clk, posedge areset)
+        begin
+            if(areset)
+                state <= WL;
+            else
+                begin
+                	state <= next_state;
+                    if((state == FR) | (state == FL))
+                    	count <= count + 1;
+                    else 
+                        count <= 0;
+                end
+        end
+    
+    //output logic
+    assign walk_left = (state == WL);
+    assign walk_right = (state == WR);
+    assign aaah = (state == FL) |(state == FR);
+    assign digging = (state == DL) | (state == DR);
+endmodule
+
+
diff --git a/7 - Sequential Logic/5 - Finite State Machines/11 - FsmOneHot.v b/7 - Sequential Logic/5 - Finite State Machines/11 - FsmOneHot.v
new file mode 100644
index 0000000..453f89d
--- /dev/null
+++ b/7 - Sequential Logic/5 - Finite State Machines/11 - FsmOneHot.v	
@@ -0,0 +1,25 @@
+module top_module(
+    input in,
+    input [9:0] state,
+    output [9:0] next_state,
+    output out1,
+    output out2);
+    
+    //State transition logic
+    
+    assign next_state[0] = (state[0] & ~in) | (state[1] & ~in) | (state[2] & ~in) | (state[3] & ~in) | (state[4] & ~in) | (state[7] & ~in) | (state[8] & ~in) | (state[9] & ~in);
+    assign next_state[1] = (state[0] & in) | (state[8] &in) | (state[9] & in);
+    assign next_state[2] = state[1] & in;
+    assign next_state[3] = state[2] & in;
+    assign next_state[4] = state[3] & in;
+    assign next_state[5] = state[4] & in;
+    assign next_state[6] = state[5] & in;
+    assign next_state[7] = (state[6] & in) | (state[7] & in);
+    assign next_state[8] = state[5] & ~in;
+    assign next_state[9] = state[6] & ~in;
+   
+    //Output logic
+    assign out1 = (state[8] == 1) | (state[9] == 1);
+    assign out2 = (state[9] ==1) | (state[7] == 1);
+    
+endmodule
diff --git a/7 - Sequential Logic/5 - Finite State Machines/12 - PS2 Packet Parser.v b/7 - Sequential Logic/5 - Finite State Machines/12 - PS2 Packet Parser.v
new file mode 100644
index 0000000..e5bb89c
--- /dev/null
+++ b/7 - Sequential Logic/5 - Finite State Machines/12 - PS2 Packet Parser.v	
@@ -0,0 +1,35 @@
+module top_module(
+    input clk,
+    input [7:0] in,
+    input reset,    // Synchronous reset
+    output done); //
+
+    parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3;
+    reg [1:0] state, next_state;
+    
+    // State transition logic (combinational)
+    always @(*)
+        begin
+            case(state)
+                S0: next_state = in[3] ? S1 : S0;
+                S1: next_state = S2;
+                S2: next_state = S3;
+                S3: next_state = in[3] ? S1 : S0;
+                default: next_state = state;
+            endcase
+        end
+
+    // State flip-flops (sequential)
+    always @(posedge clk)
+        begin
+            if(reset)
+                state <= S0;
+            else
+                state <= next_state;
+        end
+ 
+    // Output logic
+    assign done = (state == S3);
+
+endmodule
+
diff --git a/7 - Sequential Logic/5 - Finite State Machines/13 - PS2 PAcket Parser DataPath.v b/7 - Sequential Logic/5 - Finite State Machines/13 - PS2 PAcket Parser DataPath.v
new file mode 100644
index 0000000..44dcc08
--- /dev/null
+++ b/7 - Sequential Logic/5 - Finite State Machines/13 - PS2 PAcket Parser DataPath.v	
@@ -0,0 +1,45 @@
+module top_module(
+    input clk,
+    input [7:0] in,
+    input reset,    // Synchronous reset
+    output [23:0] out_bytes,
+    output done); //
+
+    // FSM from fsm_ps2
+
+    parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3;
+    reg [1:0] state, next_state;
+    reg [23:0] out_data;
+    
+    // State transition logic (combinational)
+    always @(*)
+        begin
+            case(state)
+            	S0: next_state = in[3] ? S1 : S0;
+            	S1: next_state = S2;
+            	S2: next_state = S3;
+            	S3: next_state = in[3] ? S1 : S0;
+            	default: next_state = state;
+            endcase
+        end
+
+    // State flip-flops (sequential)
+    always @(posedge clk)
+        begin
+            if(reset)
+                state <= S0;
+            else
+                begin
+                	state <= next_state;
+                    out_data <= {out_data[15:0],in};
+                end
+        end
+ 
+    // Output logic
+    assign done = (state == S3);
+
+    // New: Datapath to store incoming bytes.
+    assign out_bytes = done ? out_data : 24'bx;
+
+endmodule
+
diff --git a/7 - Sequential Logic/5 - Finite State Machines/14 - Serial Receiver.v b/7 - Sequential Logic/5 - Finite State Machines/14 - Serial Receiver.v
new file mode 100644
index 0000000..56ec74a
--- /dev/null
+++ b/7 - Sequential Logic/5 - Finite State Machines/14 - Serial Receiver.v	
@@ -0,0 +1,54 @@
+module top_module(
+    input clk,
+    input in,
+    input reset,    // Synchronous reset
+    output done
+); 
+    integer count;
+    parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3, S4 = 4; //S3 = Done
+    reg [2:0] state, next_state;
+    
+    always @ (*)
+        begin
+            case(state)
+                S0: if(~in)
+                    next_state = S1;
+                else
+                    next_state = S0;
+                S1: if(count >= 7)
+                    next_state = S2;
+                else
+                    next_state = S1;
+                S2: if(in)
+                    next_state = S3;
+                else
+                    next_state = S4;
+                S3: if(~in)
+                    next_state = S1;
+                else
+                    next_state = S0;
+                S4: if(in)
+                    next_state = S0;
+                else
+                    next_state = S4;
+                default: next_state = state;
+            endcase
+        end
+    
+    always @(posedge clk)
+        begin
+            if(reset)
+                state <= S0;
+            else
+                begin
+                state <= next_state;
+                    if(state != S1)
+                        count <= 0;
+                    else
+                    	count <= count + 1;
+                end
+        end
+
+    assign done = (state == S3);
+    
+endmodule
diff --git a/7 - Sequential Logic/5 - Finite State Machines/15 - Serial Receiver DataPath.v b/7 - Sequential Logic/5 - Finite State Machines/15 - Serial Receiver DataPath.v
new file mode 100644
index 0000000..c278cf6
--- /dev/null
+++ b/7 - Sequential Logic/5 - Finite State Machines/15 - Serial Receiver DataPath.v	
@@ -0,0 +1,64 @@
+module top_module(
+    input clk,
+    input in,
+    input reset,    // Synchronous reset
+    output [7:0] out_byte,
+    output done
+); //
+
+    // Use FSM from Fsm_serial
+    integer count;
+    parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3, S4 = 4; //S3 = Done
+    reg [2:0] state, next_state;
+    reg [7:0] data;
+    
+    always @ (*)
+        begin
+            case(state)
+                S0: if(~in)
+                    next_state = S1;
+                else
+                    next_state = S0;
+                S1: if(count >= 7)
+                    next_state = S2;
+                else
+                    next_state = S1;
+                S2: if(in)
+                    next_state = S3;
+                else
+                    next_state = S4;
+                S3: if(~in)
+                    next_state = S1;
+                else
+                    next_state = S0;
+                S4: if(in)
+                    next_state = S0;
+                else
+                    next_state = S4;
+                default: next_state = state;
+            endcase
+        end
+    
+    always @(posedge clk)
+        begin
+            if(reset)
+                state <= S0;
+            else
+                begin
+                	state <= next_state;
+                    if(state != S1)
+                        count <= 0;
+                    else
+                        begin
+                    		count <= count + 1;
+                            data <= {in,data[7:1]};
+                        end
+                end
+        end
+
+    assign done = (state == S3);
+
+    // New: Datapath to latch input bits.
+    assign out_byte = done ? data : 8'bx ;
+
+endmodule
diff --git a/7 - Sequential Logic/5 - Finite State Machines/16 - Serial Receiver Parity Check.v.v b/7 - Sequential Logic/5 - Finite State Machines/16 - Serial Receiver Parity Check.v.v
new file mode 100644
index 0000000..01089da
--- /dev/null
+++ b/7 - Sequential Logic/5 - Finite State Machines/16 - Serial Receiver Parity Check.v.v	
@@ -0,0 +1,71 @@
+module top_module(
+    input clk,
+    input in,
+    input reset,    // Synchronous reset
+    output [7:0] out_byte,
+    output done
+); //
+
+    // Modify FSM and datapath from Fsm_serialdata
+    integer count;
+    parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3, S4 = 4, S5 = 5; //S3 = Done
+    reg [2:0] state, next_state;
+    reg [7:0] data;
+    wire odd_parity;
+    wire reset_TFF;
+    
+    assign reset_TFF = (state == S0);
+    parity parity_check(clk,reset_TFF,in,odd_parity);
+    
+    always @ (*)
+        begin
+            case(state)
+                S0: if(~in)
+                    	next_state = S1;
+                	else
+                    	next_state = S0;
+                S1: if(count == 7)
+                    	next_state = S2;
+                	else	
+                    	next_state = S1;
+                S2: if ((~odd_parity && in) || (odd_parity && ~in))
+                    	next_state = S3;
+                	else
+                        next_state = S5; 
+                S3: if(in)
+                    	next_state = S4;
+                	else
+                    	next_state = S5;
+                S4: if(~in)
+                    	next_state = S1;
+                	else
+                    	next_state = S0;
+                S5: if(in)
+                    	next_state = S0;
+                	else
+                    	next_state = S5;
+                default: next_state = state;
+            endcase
+        end
+    
+    always @(posedge clk)
+        begin
+            if(reset)
+                state <= S0;
+            else
+                begin
+                	state <= next_state;
+                    if(state != S1)
+                        count <= 0;
+                    else
+                        begin
+                    		count <= count + 1;
+                            data <= {in,data[7:1]};
+                        end
+                end
+        end
+
+    assign done = (state == S4);
+    assign out_byte = done ? data : 8'bx ;
+
+endmodule
diff --git a/7 - Sequential Logic/5 - Finite State Machines/17 - Sequence Recognition.v b/7 - Sequential Logic/5 - Finite State Machines/17 - Sequence Recognition.v
new file mode 100644
index 0000000..6f8cc9d
--- /dev/null
+++ b/7 - Sequential Logic/5 - Finite State Machines/17 - Sequence Recognition.v	
@@ -0,0 +1,57 @@
+module top_module(
+    input clk,
+    input reset,    // Synchronous reset
+    input in,
+    output disc,
+    output flag,
+    output err);
+    
+    parameter S1 = 1, S2 = 2, S3 = 3, S4 = 4, S5 = 5, S6 = 6, S7 = 7, S8 = 8, S9 = 9, S10 = 10;
+    reg [3:0] state, nextState;
+    
+    //state  transistion
+    always @ (*)
+        begin
+            case(state)
+                S1: nextState = in?S2:S1;
+                S2: nextState = in?S3:S1;
+                S3: nextState = in?S4:S1;
+                S4: nextState = in?S5:S1;
+                S5: nextState = in?S6:S1;
+                S6: nextState = in?S8:S7;
+                S7: nextState = in?S2:S1;
+                S8: nextState = in?S10:S9;
+                S9: nextState = in?S2:S1;
+                S10:nextState = in?S10:S1;
+                default: nextState = state;
+            endcase
+        end
+    
+    //sequential block
+    always@(posedge clk)
+        begin
+            if(reset)
+                state <= S1;
+            else
+                state <= nextState;
+        end
+    
+    //outputs
+    always@(*)
+        begin
+            disc = 0;
+            flag = 0;
+            err = 0;
+            case(state)
+                S7: disc = 1;
+                S9: flag = 1;
+                S10: err = 1;
+                default: begin
+                    disc = 0;
+                    flag = 0;
+                    err = 0;
+                end
+            endcase
+        end
+
+endmodule
diff --git a/7 - Sequential Logic/5 - Finite State Machines/18 - Mealey FSM.v b/7 - Sequential Logic/5 - Finite State Machines/18 - Mealey FSM.v
new file mode 100644
index 0000000..8da585b
--- /dev/null
+++ b/7 - Sequential Logic/5 - Finite State Machines/18 - Mealey FSM.v	
@@ -0,0 +1,58 @@
+module top_module (
+    input clk,
+    input aresetn,    // Asynchronous active-low reset
+    input x,
+    output z ); 
+    
+    parameter S1 = 1, S2 = 2, S3 = 3;
+    reg [1:0] state, nextState;
+    
+    always @ (*)
+        begin
+            case(state)
+                S1: if(x)
+                    	begin
+                            nextState = S2;
+                            z = 0;
+                        end
+                	else
+                        begin
+                            nextState = S1;
+                            z = 0;
+                        end
+                S2: if(x)
+                    	begin
+                            nextState = S2;
+                            z = 0;
+                        end
+                	else
+                        begin
+                            nextState = S3;
+                            z = 0;
+                        end
+                S3: if(x)
+                    	begin
+                            nextState = S2;
+                            z = 1;
+                        end
+                	else
+                        begin
+                            nextState = S1;
+                            z = 0;
+                        end
+                default: begin
+                    nextState = state;
+                    z = 0;
+                end
+            endcase
+        end
+    
+    always @ (posedge clk, negedge aresetn)
+        begin
+            if(~aresetn)
+                state <= S1;
+            else
+                state <= nextState;
+        end
+
+endmodule
diff --git a/7 - Sequential Logic/5 - Finite State Machines/2 - Simple FSM1 Asynch.v b/7 - Sequential Logic/5 - Finite State Machines/2 - Simple FSM1 Asynch.v
new file mode 100644
index 0000000..bc6c380
--- /dev/null
+++ b/7 - Sequential Logic/5 - Finite State Machines/2 - Simple FSM1 Asynch.v	
@@ -0,0 +1,30 @@
+module top_module(
+    input clk,
+    input areset,    // Asynchronous reset to state B
+    input in,
+    output out);//  
+
+    parameter A=0, B=1; 
+    reg state, next_state;
+
+    always @(*) begin    // This is a combinational always block
+        // State transition logic
+        case(state)
+            A : next_state = in ? A : B;
+            B : next_state = in ? B : A;
+        endcase
+    end
+
+    always @(posedge clk, posedge areset) begin    // This is a sequential always block
+        // State flip-flops with asynchronous reset
+        if(areset)
+            state <= B;
+        else
+            state <= next_state;
+    end
+
+    // Output logic
+    assign out = (state == B);
+
+endmodule
+
diff --git a/7 - Sequential Logic/5 - Finite State Machines/3 - Simple FSM2 Synch.v b/7 - Sequential Logic/5 - Finite State Machines/3 - Simple FSM2 Synch.v
new file mode 100644
index 0000000..f1b666c
--- /dev/null
+++ b/7 - Sequential Logic/5 - Finite State Machines/3 - Simple FSM2 Synch.v	
@@ -0,0 +1,31 @@
+module top_module(
+    input clk,
+    input reset,    // Synchronous reset to OFF
+    input j,
+    input k,
+    output out); //  
+
+    parameter OFF=0, ON=1; 
+    reg state, next_state;
+
+    always @(*) begin
+        // State transition logic
+        case(state)
+            ON : next_state = k ? OFF : ON;
+            OFF: next_state = j ? ON : OFF;
+        endcase
+    end
+
+    always @(posedge clk) begin
+        // State flip-flops with synchronous reset
+        if(reset)
+            state <= OFF;
+        else
+            state <= next_state
+    end
+
+    // Output logic
+            assign out = (state == ON);
+
+endmodule
+
diff --git a/7 - Sequential Logic/5 - Finite State Machines/4 - Simple State Transition3.v b/7 - Sequential Logic/5 - Finite State Machines/4 - Simple State Transition3.v
new file mode 100644
index 0000000..f47ae30
--- /dev/null
+++ b/7 - Sequential Logic/5 - Finite State Machines/4 - Simple State Transition3.v	
@@ -0,0 +1,31 @@
+module top_module(
+    input in,
+    input [1:0] state,
+    output [1:0] next_state,
+    output out); //
+
+    parameter A=0, B=1, C=2, D=3;
+
+    // State transition logic: next_state = f(state, in)
+    always @ (*)
+        begin
+            case(state)
+                A: next_state = in ? B : A;
+                B: next_state = in ? B : C;
+                C: next_state = in ? D : A;
+                default: next_state = in ? B : C;
+            endcase
+        end
+
+    // Output logic:  out = f(state) for a Moore state machine
+    always @ (*)
+        begin
+            case(state)
+                A: out = 0;
+                B: out = 0;
+                C: out = 0;
+                default: out = 1;
+            endcase
+        end
+endmodule
+
diff --git a/7 - Sequential Logic/5 - Finite State Machines/5 - Fsm3OneHot.v b/7 - Sequential Logic/5 - Finite State Machines/5 - Fsm3OneHot.v
new file mode 100644
index 0000000..e575503
--- /dev/null
+++ b/7 - Sequential Logic/5 - Finite State Machines/5 - Fsm3OneHot.v	
@@ -0,0 +1,19 @@
+module top_module(
+    input in,
+    input [3:0] state,
+    output [3:0] next_state,
+    output out); //
+
+    parameter A=0, B=1, C=2, D=3;
+
+    // State transition logic: Derive an equation for each state flip-flop.
+    assign next_state[A] = (state[0] & ~in) | (state[2] & ~in);
+    assign next_state[B] = (state[0] & in) | (state[1] & in) | (state[3] & in);
+    assign next_state[C] = (state[1] & ~in) | (state[3] & ~in);
+    assign next_state[D] = state[2] & in;
+
+    // Output logic: 
+    assign out = state[3];
+
+endmodule
+
diff --git a/7 - Sequential Logic/5 - Finite State Machines/6 - Moore FSM.v b/7 - Sequential Logic/5 - Finite State Machines/6 - Moore FSM.v
new file mode 100644
index 0000000..8647ec9
--- /dev/null
+++ b/7 - Sequential Logic/5 - Finite State Machines/6 - Moore FSM.v	
@@ -0,0 +1,114 @@
+module top_module (
+    input clk,
+    input reset,
+    input [3:1] s,
+    output fr3,
+    output fr2,
+    output fr1,
+    output dfr
+); 
+    
+    parameter S0 = 3'b000, S1 = 3'b001, S2 = 3'b010, S3 = 3'b011, S4 = 3'b100, S5 = 3'b101;
+    reg [2:0] next_state, state;
+    
+    //State transistion logic
+    
+    always @ (*)
+        begin
+            case(state)
+                S0: if (s[1] & ~s[2] & ~s[3])
+                    	next_state = S1;
+                	else
+                        next_state = state;
+                S1:	if (s[1] & s[2] & ~s[3])
+                    	next_state = S2;
+                else if (~s[1] & ~s[2] & ~s[3])
+                    	next_state = S0;
+                else
+                    	next_state = state;
+                S2:	if (s[1] & s[2] & s[3])
+                    	next_state = S3;
+                else if (s[1] & ~s[2] & ~s[3])
+                    	next_state = S5;
+                else
+                    	next_state = state;
+                S3: if (s[1] & s[2] & ~s[3])
+                    	next_state = S4;
+                else
+                    	next_state = state;
+                S4:	if (s[1] & ~s[2] & ~s[3])
+                    	next_state = S5;
+                else if (s[1] & s[2] & s[3])
+                    	next_state = S3;
+                else
+                    	next_state = state;
+                S5: if (~s[1] & ~s[2] & ~s[3])
+                    	next_state = S0;
+                else if (s[1] & s[2] & ~s[3])
+                    	next_state = S2;
+                else
+                    next_state = state;
+                default: next_state = state;
+            endcase
+        end
+    
+    
+    //Current state logic
+    always @ (posedge clk)
+        begin
+            if(reset)
+            	state <= S0;
+            else
+                state <= next_state;
+        end
+    
+    //Output Logic
+    
+    always @ (*)
+        begin
+            case(state)
+                S0: begin
+                    dfr = 1'b1;
+                    fr1 = 1'b1;
+                    fr2 = 1'b1;
+                    fr3 = 1'b1;
+                end
+                S1: begin
+                    dfr = 1'b0;
+                    fr1 = 1'b1;
+                    fr2 = 1'b1;
+                    fr3 = 1'b0;
+                end
+                S2: begin
+                    dfr = 1'b0;
+                    fr1 = 1'b1;
+                    fr2 = 1'b0;
+                    fr3 = 1'b0;
+                end
+                S3: begin
+                    dfr = 1'b0;
+                    fr1 = 1'b0;
+                    fr2 = 1'b0;
+                    fr3 = 1'b0;
+                end
+                S4: begin
+                    dfr = 1'b1;
+                    fr1 = 1'b1;
+                    fr2 = 1'b0;
+                    fr3 = 1'b0;
+                end
+                S5: begin
+                    dfr = 1'b1;
+                    fr1 = 1'b1;
+                    fr2 = 1'b1;
+                    fr3 = 1'b0;
+                end
+                default: begin
+                    dfr = 0;
+                    fr1 = 0;
+                    fr2 = 0;
+                    fr3 = 0;
+                end
+            endcase
+        end
+endmodule
diff --git a/7 - Sequential Logic/5 - Finite State Machines/7 - Lemmings1.v b/7 - Sequential Logic/5 - Finite State Machines/7 - Lemmings1.v
new file mode 100644
index 0000000..760babd
--- /dev/null
+++ b/7 - Sequential Logic/5 - Finite State Machines/7 - Lemmings1.v	
@@ -0,0 +1,39 @@
+module top_module(
+    input clk,
+    input areset,    // Freshly brainwashed Lemmings walk left.
+    input bump_left,
+    input bump_right,
+    output walk_left,
+    output walk_right); //  
+
+    parameter LEFT=0, RIGHT=1;
+    reg state, next_state;
+
+    always @(*) begin
+        // State transition logic
+        case(state)
+            LEFT: if (bump_left)
+                	next_state = RIGHT;
+            	else
+                    next_state = LEFT;
+            RIGHT: if (bump_right)
+                	next_state = LEFT;
+            	else
+                    next_state = RIGHT;
+            default: next_state = state;
+        endcase
+    end
+
+    always @(posedge clk, posedge areset) begin
+        // State flip-flops with asynchronous reset
+        if(areset)
+            state <= LEFT;
+        else
+            state <= next_state;
+    end
+
+    // Output logic
+    assign walk_left = (state == LEFT);
+    assign walk_right = (state == RIGHT);
+
+endmodule
diff --git a/7 - Sequential Logic/5 - Finite State Machines/8 - Lemmings2.v b/7 - Sequential Logic/5 - Finite State Machines/8 - Lemmings2.v
new file mode 100644
index 0000000..d83ec69
--- /dev/null
+++ b/7 - Sequential Logic/5 - Finite State Machines/8 - Lemmings2.v	
@@ -0,0 +1,57 @@
+module top_module(
+    input clk,
+    input areset,    // Freshly brainwashed Lemmings walk left.
+    input bump_left,
+    input bump_right,
+    input ground,
+    output walk_left,
+    output walk_right,
+    output aaah ); 
+
+    parameter WL = 0, WR = 1, FL = 2, FR = 3;
+    reg [1:0] state, next_state;
+    
+    // State transition logic
+    always @ (*)
+        begin
+            case(state)
+                WL: if(~ground)
+                    	next_state = FL;
+                else if(bump_left)
+                    	next_state = WR;
+                else
+                    	next_state = state;
+                WR: if(~ground)
+                    	next_state = FR;
+                else if(bump_right)
+                    	next_state = WL;
+                else
+                    	next_state = state;
+                FL: if(ground)
+                    	next_state = WL;
+                	else
+                        next_state = FL;
+                FR:	if(ground)
+                    	next_state = WR;
+                	else
+                        next_state = FR;
+                default: next_state = state;
+            endcase
+        end
+    
+    //Sequential logic
+    always @ (posedge clk, posedge areset)
+        begin
+            if(areset)
+                state <= WL;
+            else
+                state <= next_state;
+        end
+    
+    //output logic
+    assign walk_left = (state == WL);
+    assign walk_right = (state == WR);
+    assign aaah = (state == FL) |(state == FR);
+endmodule
+
+
diff --git a/7 - Sequential Logic/5 - Finite State Machines/9 - Lemmings3.v b/7 - Sequential Logic/5 - Finite State Machines/9 - Lemmings3.v
new file mode 100644
index 0000000..a05085e
--- /dev/null
+++ b/7 - Sequential Logic/5 - Finite State Machines/9 - Lemmings3.v	
@@ -0,0 +1,72 @@
+module top_module(
+	input clk,
+    input areset,    // Freshly brainwashed Lemmings walk left.
+    input bump_left,
+    input bump_right,
+    input ground,
+    input dig,
+    output walk_left,
+    output walk_right,
+    output aaah,
+    output digging ); 
+
+    parameter WL = 0, WR = 1, DL = 2, DR = 3, FL = 4, FR = 5;
+    reg [3:0] state, next_state;
+    
+    // State transition logic
+    always @ (*)
+        begin
+            case(state)
+                WL: if(~ground)
+                    next_state = FL;
+                else if(dig)
+                    next_state = DL;
+                else if(bump_left)
+                    next_state = WR;
+                else
+                    next_state = state;
+                WR: if(~ground)
+                    next_state = FR;
+                else if(dig)
+                    next_state = DR;
+                else if(bump_right)
+                    next_state = WL;
+                else
+                    next_state = state;
+                DL: if(~ground)
+                    next_state = FL;
+                else
+                    next_state = state;
+                DR: if(~ground)
+                    next_state = FR;
+                else
+                    next_state = state;
+                FL: if(ground)
+                    next_state = WL;
+                else
+                     next_state = FL;
+                FR:	if(ground)
+                    next_state = WR;
+                else
+                    next_state = FR;
+                default: next_state = state;
+            endcase
+        end
+    
+    //Sequential logic
+    always @ (posedge clk, posedge areset)
+        begin
+            if(areset)
+                state <= WL;
+            else
+                state <= next_state;
+        end
+    
+    //output logic
+    assign walk_left = (state == WL);
+    assign walk_right = (state == WR);
+    assign aaah = (state == FL) |(state == FR);
+    assign digging = (state == DL) | (state == DR);
+ endmodule
+
+