bit patterns of shift immediate instructions

[miguelbarao]

In the file riscv-sodor/src/common/instructions.scala, I noticed that the bit patterns of the shift immediate instructions slli, srli and srai only have 6 bits on the left while the specification has 7.
Is this an error?

[ccelio]

I don't think I understand what you are asking. Can you elaborate?

As background information, the instructions.scala is auto-generated from riscv-tools infrastructure which is also used by other chisel processors, such as (https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/rocket/Instructions.scala) (although sodor may be out of date a tad on the privileged stuff).

[miguelbarao]

Nevermind, my mistake. The bit patterns apply to RV64 while I was looking to RV32. It's correct.