Converted Z80 to use emulator-hal traits (#7)

* Converted Z80 to use emulator-hal traits

* Updated emulator-hal

* Added a hacky Signalable trait to replace the Z80 signals

* Minor fixes

* Fixed timing tests and added no io tests option

* Fixed genesis Z80 bus issue

* Fixed addressing for BusAccess impl of Z80

* Fixed tests and clippy lints

Author: transistorfet

Cargo.lock

@@ -21,8 +21,10 @@ For more about the Sega Genesis support, check out this series I wrote about imp
 I've also generated rustdocs of the workspace. All the various crates within moa
 are listed in the crates section in the sidebar on the left. There's not a lot
 of doc comments in the code yet but I plan to eventually write more:
-[rustdocs for moa_core](http://jabberwocky.ca/moa/doc/moa_core/)
-[rustdocs for ym2612](http://jabberwocky.ca/moa/doc/moa_peripherals_yamaha/ym2612/index.html)
+[moa_core](http://jabberwocky.ca/moa/doc/moa_core/)
+[moa_m68k](http://jabberwocky.ca/moa/doc/moa_m68k/)
+[moa_z80](http://jabberwocky.ca/moa/doc/moa_z80/)
+[ym2612](http://jabberwocky.ca/moa/doc/moa_peripherals_yamaha/ym2612/index.html)
 
 This repository uses submodules, so make sure to clone with
 ```sh

README.md

@@ -8,4 +8,4 @@ log = "0.4"
 femtos = "0.1"
 thiserror = "1.0"
 moa-host = { path = "../libraries/host" }
-emulator-hal = { path = "../libraries/emulator-hal/emulator-hal" }
+emulator-hal = { path = "../libraries/emulator-hal/emulator-hal", features = ["femtos"] }

emulator/core/Cargo.toml

@@ -171,6 +171,16 @@ pub trait Inspectable {
     fn inspect(&mut self, system: &System, args: &[&str]) -> Result<(), Error>;
 }
 
+#[derive(Copy, Clone, Debug, PartialEq, Eq)]
+pub enum Signal {
+    Reset,
+    BusRequest,
+}
+
+pub trait Signalable {
+    fn set_signal(&mut self, signal: Signal, flag: bool) -> Result<(), Error>;
+    fn signal(&mut self, signal: Signal) -> Option<bool>;
+}
 
 pub trait Transmutable {
     #[inline]
@@ -197,6 +207,11 @@ pub trait Transmutable {
     fn as_inspectable(&mut self) -> Option<&mut dyn Inspectable> {
         None
     }
+
+    #[inline]
+    fn as_signalable(&mut self) -> Option<&mut dyn Signalable> {
+        None
+    }
 }
 
 pub type TransmutableBox = Rc<RefCell<Box<dyn Transmutable>>>;

emulator/core/src/devices.rs

@@ -71,3 +71,9 @@ impl<E> From<HostError<E>> for Error {
         Self::Other("other".to_string())
     }
 }
+
+impl From<fmt::Error> for Error {
+    fn from(err: fmt::Error) -> Self {
+        Self::Other(format!("{:?}", err))
+    }
+}

emulator/core/src/error.rs

@@ -7,7 +7,8 @@ mod memory;
 mod system;
 
 pub use crate::devices::{
-    Address, Addressable, Steppable, Interruptable, Debuggable, Inspectable, Transmutable, TransmutableBox, Device,
+    Address, Addressable, Steppable, Interruptable, Debuggable, Inspectable, Signalable, Signal, Transmutable, TransmutableBox,
+    Device,
 };
 pub use crate::devices::{
     read_beu16, read_beu32, read_leu16, read_leu32, write_beu16, write_beu32, write_leu16, write_leu32, wrap_transmutable,
@@ -17,4 +18,4 @@ pub use crate::interrupts::InterruptController;
 pub use crate::memory::{MemoryBlock, AddressTranslator, AddressRepeater, Bus, BusPort, dump_slice, dump_memory};
 pub use crate::system::System;
 
-pub use emulator_hal::bus::{BusAccess};
+pub use emulator_hal::BusAccess;

emulator/core/src/lib.rs

@@ -4,6 +4,7 @@ use std::rc::Rc;
 use std::cell::RefCell;
 use std::fmt::Write;
 use femtos::Instant;
+use emulator_hal::{self, BusAccess, ErrorType};
 
 use crate::error::Error;
 use crate::devices::{Address, Addressable, Transmutable, Device, read_beu16};
@@ -236,7 +237,7 @@ impl Bus {
 
             let to = if count < 16 { count / 2 } else { 8 };
             for _ in 0..to {
-                let word = self.read_beu16(clock, addr);
+                let word = Addressable::read_beu16(self, clock, addr);
                 if word.is_err() {
                     println!("{}", line);
                     return;
@@ -353,7 +354,7 @@ impl Addressable for BusPort {
         for i in (0..data.len()).step_by(self.data_width as usize) {
             let addr_index = (addr + i as Address) & self.address_mask;
             let end = cmp::min(i + self.data_width as usize, data.len());
-            subdevice.read(clock, addr_index, &mut data[i..end])?;
+            Addressable::read(&mut *subdevice, clock, addr_index, &mut data[i..end])?;
         }
         Ok(())
     }
@@ -364,7 +365,7 @@ impl Addressable for BusPort {
         for i in (0..data.len()).step_by(self.data_width as usize) {
             let addr_index = (addr + i as Address) & self.address_mask;
             let end = cmp::min(i + self.data_width as usize, data.len());
-            subdevice.write(clock, addr_index, &data[i..end])?;
+            Addressable::write(&mut *subdevice, clock, addr_index, &data[i..end])?;
         }
         Ok(())
     }
@@ -412,9 +413,7 @@ where
     }
 }
 
-use emulator_hal::bus::{self, BusAccess};
-
-impl bus::Error for Error {}
+impl ErrorType for Error {}
 
 impl BusAccess<u64> for &mut dyn Addressable {
     type Instant = Instant;
@@ -430,3 +429,18 @@ impl BusAccess<u64> for &mut dyn Addressable {
         Ok(data.len())
     }
 }
+
+impl BusAccess<u64> for Bus {
+    type Instant = Instant;
+    type Error = Error;
+
+    fn read(&mut self, now: Instant, addr: Address, data: &mut [u8]) -> Result<usize, Self::Error> {
+        Addressable::read(self, now, addr, data)?;
+        Ok(data.len())
+    }
+
+    fn write(&mut self, now: Instant, addr: Address, data: &[u8]) -> Result<usize, Self::Error> {
+        Addressable::write(self, now, addr, data)?;
+        Ok(data.len())
+    }
+}

emulator/core/src/memory.rs

@@ -2,9 +2,7 @@
 
 use core::fmt;
 
-use emulator_hal::time;
-use emulator_hal::bus::{self, BusAccess};
-use emulator_hal::step::{Inspect, Debug};
+use emulator_hal::{Instant as BusInstant, ErrorType, BusAccess, Inspect, Debug};
 
 use crate::{M68k, M68kError, M68kAddress, M68kCycleExecutor};
 
@@ -31,7 +29,7 @@ pub enum M68kInfo {
 impl<Bus, BusError, Instant, Writer> Inspect<M68kAddress, Bus, Writer> for M68k<Instant>
 where
     Bus: BusAccess<M68kAddress, Instant = Instant, Error = BusError>,
-    BusError: bus::Error,
+    BusError: ErrorType,
     Writer: fmt::Write,
 {
     type InfoType = M68kInfo;
@@ -60,8 +58,8 @@ where
 impl<Bus, BusError, Instant, Writer> Debug<M68kAddress, Bus, Writer> for M68k<Instant>
 where
     Bus: BusAccess<M68kAddress, Instant = Instant, Error = BusError>,
-    BusError: bus::Error,
-    Instant: time::Instant,
+    BusError: ErrorType,
+    Instant: BusInstant,
     Writer: fmt::Write,
 {
     // TODO this should be a new type

emulator/cpus/m68k/src/debugger.rs

@@ -1,7 +1,7 @@
 // Instruction Decoding
 
 use core::marker::PhantomData;
-use emulator_hal::bus::BusAccess;
+use emulator_hal::BusAccess;
 
 use crate::{M68kType, M68kError, M68kBusPort, M68kAddress, Exceptions};
 use crate::instructions::{

emulator/cpus/m68k/src/decode.rs

@@ -1,8 +1,6 @@
 // Instruction Execution
 
-use emulator_hal::time;
-use emulator_hal::step::Step;
-use emulator_hal::bus::{self, BusAccess};
+use emulator_hal::{Instant as BusInstant, ErrorType, BusAccess, Step};
 
 use crate::{M68k, M68kType, M68kError, M68kState};
 use crate::state::{Status, Flags, Exceptions, InterruptPriority};
@@ -35,7 +33,7 @@ pub struct M68kCycle<Instant> {
 
 impl<Instant> M68kCycle<Instant>
 where
-    Instant: time::Instant,
+    Instant: BusInstant,
 {
     #[inline]
     pub fn default(cputype: M68kType, data_width: u8) -> Self {
@@ -77,8 +75,8 @@ where
 impl<Bus, BusError, Instant> Step<M68kAddress, Bus> for M68k<Instant>
 where
     Bus: BusAccess<M68kAddress, Instant = Instant, Error = BusError>,
-    BusError: bus::Error,
-    Instant: time::Instant,
+    BusError: ErrorType,
+    Instant: BusInstant,
 {
     type Error = M68kError<BusError>;
 

emulator/cpus/m68k/src/execute.rs

@@ -18,4 +18,4 @@ pub use crate::memory::{M68kAddress, M68kAddressSpace, M68kBusPort};
 pub use crate::decode::{M68kDecoder, InstructionDecoding};
 pub use crate::execute::{M68kCycle, M68kCycleExecutor};
 pub use crate::timing::M68kInstructionTiming;
-//pub use crate::instructions::{Instruction, Target, Size, Sign, XRegister, BaseRegister, IndexRegister, Direction};
+pub use crate::instructions::*;

emulator/cpus/m68k/src/lib.rs

@@ -1,7 +1,6 @@
 use core::cmp;
 use core::fmt::Write;
-use emulator_hal::time;
-use emulator_hal::bus::BusAccess;
+use emulator_hal::{Instant as BusInstant, BusAccess};
 
 use crate::{M68kError, CpuInfo};
 use crate::state::Exceptions;
@@ -65,7 +64,7 @@ impl FunctionCode {
 
 impl<Instant> Default for MemoryRequest<Instant>
 where
-    Instant: time::Instant,
+    Instant: BusInstant,
 {
     fn default() -> Self {
         Self {
@@ -138,7 +137,7 @@ pub struct M68kBusPort<Instant> {
 
 impl<Instant> Default for M68kBusPort<Instant>
 where
-    Instant: time::Instant,
+    Instant: BusInstant,
 {
     fn default() -> Self {
         Self {

emulator/cpus/m68k/src/memory.rs

@@ -1,5 +1,5 @@
 use femtos::{Instant, Duration};
-use emulator_hal::bus;
+use emulator_hal::{ErrorType, BusAdapter};
 
 use moa_core::{System, Error, Address, Steppable, Interruptable, Addressable, Debuggable, Transmutable};
 
@@ -10,8 +10,7 @@ impl Steppable for M68k<Instant> {
         let cycle = M68kCycle::new(self, system.clock);
 
         let mut bus = system.bus.borrow_mut();
-        let mut adapter: bus::BusAdapter<u32, u64, &mut dyn Addressable, Error> =
-            bus::BusAdapter::new(&mut *bus, |addr| addr as u64, |err| err);
+        let mut adapter: BusAdapter<u32, u64, &mut dyn Addressable, Error> = BusAdapter::new(&mut *bus, |addr| addr as u64);
 
         let mut executor = cycle.begin(self, &mut adapter);
         executor.check_breakpoints()?;
@@ -60,7 +59,7 @@ impl<BusError> From<Error> for M68kError<BusError> {
     }
 }
 
-impl<BusError: bus::Error> From<M68kError<BusError>> for Error {
+impl<BusError: ErrorType> From<M68kError<BusError>> for Error {
     fn from(err: M68kError<BusError>) -> Self {
         match err {
             M68kError::Halted => Self::Other("cpu halted".to_string()),
@@ -86,11 +85,17 @@ impl Debuggable for M68k<Instant> {
         }
     }
 
-    fn print_current_step(&mut self, _system: &System) -> Result<(), Error> {
+    fn print_current_step(&mut self, system: &System) -> Result<(), Error> {
+        let mut bus = system.bus.borrow_mut();
+        let mut adapter: BusAdapter<u32, u64, &mut dyn Addressable, Error> = BusAdapter::new(&mut *bus, |addr| addr as u64);
+
         // TODO this is called by the debugger, but should be called some other way
-        //let _ = self.decoder.decode_at(&mut self.bus, true, self.state.pc);
-        //self.decoder.dump_decoded(&mut self.bus);
-        //self.dump_state();
+        let mut decoder = M68kDecoder::new(self.info.chip, true, self.state.pc);
+        decoder.decode_at(&mut adapter, &mut M68kBusPort::default(), true, self.state.pc)?;
+        decoder.dump_decoded(system.clock, &mut adapter);
+        let mut writer = String::new();
+        self.dump_state(&mut writer)?;
+        println!("{}", writer);
         Ok(())
     }
 
@@ -99,8 +104,7 @@ impl Debuggable for M68k<Instant> {
         let mut memory = M68kBusPort::from_info(&self.info, system.clock);
 
         let mut bus = system.bus.borrow_mut();
-        let mut adapter: bus::BusAdapter<u32, u64, &mut dyn Addressable, Error> =
-            bus::BusAdapter::new(&mut *bus, |addr| addr as u64, |err| err);
+        let mut adapter: BusAdapter<u32, u64, &mut dyn Addressable, Error> = BusAdapter::new(&mut *bus, |addr| addr as u64);
 
         decoder.dump_disassembly(&mut adapter, &mut memory, addr as u32, count as u32);
     }

emulator/cpus/m68k/src/moa.rs

@@ -2,7 +2,7 @@
 
 use femtos::Frequency;
 use core::fmt::{self, Write};
-use emulator_hal::time;
+use emulator_hal::Instant as BusInstant;
 
 use crate::{M68kDebugger, M68kCycle};
 use crate::instructions::Target;
@@ -243,7 +243,7 @@ impl M68kState {
 
 impl<Instant> M68k<Instant>
 where
-    Instant: time::Instant,
+    Instant: BusInstant,
 {
     pub fn new(info: CpuInfo) -> Self {
         M68k {

emulator/cpus/m68k/src/state.rs

@@ -1,7 +1,7 @@
 #[cfg(test)]
 mod decode_unit_tests {
     use femtos::Instant;
-    use emulator_hal::bus::BusAccess;
+    use emulator_hal::BusAccess;
     use emulator_hal_memory::MemoryBlock;
 
     use crate::M68kType;
@@ -13,7 +13,7 @@ mod decode_unit_tests {
 
     fn run_decode_test<F>(cputype: M68kType, mut test_func: F)
     where
-        F: FnMut(&mut InstructionDecoding<'_, MemoryBlock<u32, Instant>, Instant>),
+        F: FnMut(&mut InstructionDecoding<'_, MemoryBlock<Instant>, Instant>),
     {
         let mut memory = MemoryBlock::from(vec![0; 0x0000100]);
         let mut decoder = M68kDecoder::new(cputype, true, 0);
@@ -316,8 +316,7 @@ mod decode_unit_tests {
 #[cfg(test)]
 mod execute_unit_tests {
     use femtos::{Instant, Frequency};
-    use emulator_hal::bus::BusAccess;
-    use emulator_hal::step::Step;
+    use emulator_hal::{Step, BusAccess};
     use emulator_hal_memory::MemoryBlock;
 
     use crate::{M68k, M68kType};
@@ -330,7 +329,7 @@ mod execute_unit_tests {
     #[allow(clippy::uninit_vec)]
     fn run_execute_test<F>(cputype: M68kType, mut test_func: F)
     where
-        F: FnMut(M68kCycleExecutor<&mut MemoryBlock<u32, Instant>, Instant>),
+        F: FnMut(M68kCycleExecutor<&mut MemoryBlock<Instant>, Instant>),
     {
         // Insert basic initialization
         let len = 0x10_0000;

emulator/cpus/m68k/src/tests.rs

@@ -1,5 +1,5 @@
 use femtos::{Instant, Frequency};
-use emulator_hal::bus::BusAccess;
+use emulator_hal::BusAccess;
 use emulator_hal_memory::MemoryBlock;
 
 use moa_m68k::{M68k, M68kType, M68kAddress};
@@ -64,7 +64,7 @@ const DECODE_TESTS: &'static [TestCase] = &[
 ];
 
 
-fn init_decode_test(cputype: M68kType) -> (M68k<Instant>, M68kCycle<Instant>, MemoryBlock<u32, Instant>) {
+fn init_decode_test(cputype: M68kType) -> (M68k<Instant>, M68kCycle<Instant>, MemoryBlock<Instant>) {
     // Insert basic initialization
     let len = 0x2000;
     let mut data = Vec::with_capacity(len);