Digital logic design tool and simulator
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Updated
May 28, 2024 - Java
Digital logic design tool and simulator
VUnit is a unit testing framework for VHDL/SystemVerilog
🖥️ A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
An abstraction library for interfacing EDA tools
Haskell to VHDL/Verilog/SystemVerilog compiler
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
Hardware Description Languages
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
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