Sol-1: A CPU/Computer System made from 74 series logic.
-
Updated
Jun 10, 2024 - C
Sol-1: A CPU/Computer System made from 74 series logic.
Veryl: A Modern Hardware Description Language
A (mostly) EDTASM+ compatible MC6809 Assembler using yacc/bison
High-level block designs for MIPS 32 bit processor with pipelining & forwarding controls, hazard detection, and timing. Tested and verified in EECS 112L course on Organization of Computers.
SystemVerilog to Verilog conversion
Verilator open-source SystemVerilog simulator and lint system
Designing Single-Cycle Microprocessor without Interlocked Pipeline Stages (MIPS) using Verilog.
SystemVerilog compiler and language services
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
TX only RoCEv2. Super stripped down version of a RoCEv2 endpoint.
My technical notes as bite-sized executable programs
HDL support for VS Code
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
This is my first repo adding to my github account.
Opensource DDR3 Controller
Cross EDA Abstraction and Automation
It is a project on verilog which I had learned from a course taught by Prof. Indranil Sengupta at IIT Kharagpur.
Add a description, image, and links to the verilog topic page so that developers can more easily learn about it.
To associate your repository with the verilog topic, visit your repo's landing page and select "manage topics."