BDD Gherkin implementation in native SystemVerilog, based on UVM.
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Updated
Jun 8, 2024 - SystemVerilog
BDD Gherkin implementation in native SystemVerilog, based on UVM.
🇯 JSON encoder and decoder in pure SystemVerilog
A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video pipeline with remote connectivity. For Sony, Series7 & open FPGA makers on limited budget. Augments openXC7 CI/CD, challenging its timing-savvy. Promotes the lesser-known EU boards.
Veryl: A Modern Hardware Description Language
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Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
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Examples of SystemC from the High-Level Systems Design course of the Master's Degree in Electronics at the Costa Rica Institute of Technology.
WIP: Very much a RISC-V core, written in SystemVerilog
Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
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The final product is amazing - a small and simple RISC-V processor that I implemented myself. The assignments are gradual and each stage makes use of the tools I have acquired so far.
Functional verification project for the CORE-V family of RISC-V cores.
System verilog learning journey. Here in this repo you learn about how to write system verilog test bench using verilator tool a c++ test bench. Verilator is basically a 2 state tool .
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