An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
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Updated
May 31, 2024 - Scala
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
32-bit Superscalar RISC-V CPU
Educational computer simulator on a mission to "superscalate" the study of computer architecture fundamentals
An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support for 3-5 way superscalar execution. The core is pin-to-pin compatible with the RISCY cores from PULP
A compiler, assembler, and processor.
A superscalar processor in Python
Super scalar Processor design
DUTH RISC-V Superscalar Microprocessor
Superscalar OoO RISCV processor written in Chisel
Direct Biot-Savart solver for 2D and 3D vortex blobs accelerated with Vc
Two Level Branch Predictor Simulator - EE382N Superscalar Microprocessor Architecture, Spring 2019, Assignment 4
Easy-to-implement n-body simulation kernels created using Intel's ispc and llvm/clang
Superscalar 8 bit processor made in logisim and corresponding assembly language to bit code compiler.
Repositório para as aulas, exercícios e resumos da matéria: organização e arquitetura de computadores (INE5607).
MIPS32 CPU implemented in SystemVerilog, with superscalar and branch prediction support
Out of order superscalar processor simulated in Javascript
A superscalar processor simulator written in Java as part of the Advanced Computer Architecture unit.
CS-470 Homework 1
Implementation of advanced branch predictors, including Perceptron and Combinational Two-Level Adaptive Predictors, within the SimpleScalar simulator. Showcases enhancements in prediction accuracy and dynamic branch prediction techniques. This is a project for PSU ECE 587: Advanced Computer Architecture
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