questasim
Here are 28 public repositories matching this topic...
Repurposing existing HDL tools to help writing better code
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Jun 6, 2024 - Python
RiscV Environment for Simulation (R4VES) is a generic and modular framework that eases the grunt work required in order to perform pre/post-synthesis logic and fault simulation on RISC-V cores based on Model/QuestaSim and Z01X.
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May 28, 2024 - Verilog
Fault injection environment (finjenv) of permanent hardware faults for various arithmetic circuits based on QuestaSIM logic simulator
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May 26, 2024 - Verilog
This project implements a SPI (Serial Peripheral Interface) slave module with a single port RAM block. The SPI slave module receives data from a master device and communicates with the single port RAM to store and retrieve data.
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May 21, 2024 - Verilog
This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, SystemVerilog, and SVA. The main objectives included designing modules compliant with industry standards such as APB (Advanced Peripheral Bus), memory systems, and systolic matrix multiplication.
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Apr 8, 2024 - Verilog
Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀
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Mar 3, 2024 - SystemVerilog
CPR E 381 Project: Three MIPS Processor Designs - VHDL and Waveform Simulations
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Nov 28, 2023 - Python
Latest addition to REPO : Folder with vending machine design and TB including code coverage report
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May 21, 2023 - HTML
RTL development of Quad Serial Peripheral Interface (Quad-SPI) on QuestaSim using SystemVerilog.
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Oct 19, 2022 - SystemVerilog
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