ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)
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Updated
Aug 29, 2018 - VHDL
ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)
厚本金融维权,红杉资本(沈南鹏),厚本金融(陆泳),中华财险,厦门银行。厚本金融合作伙伴包括中华财险、厦门银行、同盾科技、百融金服、易宝支付、中伦律师事务所、上海资信有限公司。
This project aims to detect ddos attack using various architecture model
Thesis: Custom Filter Designs on the Red Pitaya
System that finds the critical path of the graph of the disciplines of the Computer Science course at UnB (University of Brasília).
Imports your CIC bank accounts and transactions into your cozy cloud
listen to pcm sound over the internal pc speaker
Projeto desenvolvido como parte da avaliação da disciplina Técnicas de Programação 1 do 1¶/2019 da Universidade de Brasília - UnB do departamento de Ciência da Computação, ministrada pelo professor Cristhian Ivan Riaño Jaimes.(https://github.com/cristhianivanrj).
Inteligencia Artificial usando Common Lisp en Español.
A simple and crude CIC filter implementation in Python3 for learning purposes
Useful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.)
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