altera

Here are 186 public repositories matching this topic...

QuestIO42 / vlab

A set of PHP files, scripts and database to allow remote users to edit programs, upload code and access the serial port of real microcontrollers.

fpga digital amd logic remote intel xilinx altera

Updated Jun 7, 2024
PHP

hdl-modules / hdl-modules

Star

A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

asic fpga hardware amd vhdl intel eda rtl ip xilinx vivado altera fifo cdc axi microsemi clock-domain-crossing asynchronous-fifo axi-lite efinix

Updated Jun 7, 2024
VHDL

Charlie-Ramirez-Animation-Studios-de-MX / VHDL-Basicos

Star

Programas Basicos en Lenguaje VHDL de Diseño Logico y Diseño de Circuitos Digitales para Uso y simulacion con QuartusII y los FPGA Cyclone III de Altera (Compilados y compatibles con la FPGA EP3C16F484C6N) Para Practica en la Licenciatura de Ingenieria Electrica Electronica e Ingenieria en Computación Bajo Licencia MIT

fpga vhdl altera unam quartus vhdl-examples quartus2 altera-quartus

Updated Jun 3, 2024
VHDL

PyFPGA / pyfpga

Star

A Python package to use FPGA development tools programmatically.

python fpga amd tcl intel trellis xilinx vivado altera ise icestorm lattice microchip ghdl yosys quartus microsemi nextpnr actel libero

Updated Jun 6, 2024
Python

ua1arn / hftrx

Star

Embedded firmware for ham radio transceivers

zynq stm32 ham-radio sdr altera bare-metal cortex-a baremetal hamradio allwinner ssb cortex-a7 renesas cortex-a9 ehci stm32mp1 sdr-radio rza1 t113-s3

Updated Jun 8, 2024
C

pConst / basic_verilog

Star

Must-have verilog systemverilog modules

Updated May 28, 2024
Verilog

f32c / f32c

Star

A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz

arduino fpga mips riscv xilinx altera lattice

Updated May 27, 2024
C

drandyhaas / Haasoscope

Star

Docs, design, firmware, and software for the Haasoscope

python open-source fpga eagle open-hardware data-acquisition verilog oscilloscope altera

Updated May 24, 2024
Verilog

robseb / meta-intelfpga

Star

Yocto Project BSP meta-layer for Intel (ALTERA) SoC-FPGAs (SoCFPGA) - with step by step guide

linux-distribution yocto-layer altera yocto-meta development-tools cyclone-v intel-fpga arria-v arria10 intel-soc-fpgas fpga-configuration soc-fpga soc-fpga-linux fpga-fabric bsp-layer rsyocto

Updated May 23, 2024
BitBake

TanumaHideki / ReLM-PoC

Star

ReLM is the soft-core multiprocessor technology based on the unique memory architecture, enabling users to build a high-performance microcontroller on a relatively small FPGA board.

game python fpga multiprocessing parallel parallel-computing verilog altera parallel-processing multiprocessor softcore altera-fpga relm register-less bubble-estate

Updated May 23, 2024
Python

otaviocmaciel / 7-segment-VHDL

Star

4 digits 7-segment controller VHDL

development fpga vhdl verilog altera fpga-board

Updated May 22, 2024
VHDL

MJoergen / HyperRAM

Star

Portable HyperRAM controller

fpga vhdl intel xilinx vivado altera lattice modelsim questasim avalon quartus artix questa hyperram

Updated May 22, 2024
VHDL

otaviocmaciel / DAC-MCP482x-VHDL-core

Star

MCP482x DAC Family VHDL Core

development fpga vhdl verilog altera fpga-board

Updated May 21, 2024
VHDL

olofk / edalize

Star

An abstraction library for interfacing EDA tools

Updated May 17, 2024
Python

har-in-air / FPGA_STEREO_CROSSOVER

Star

Stereo digital 2-way crossover filters processing I2S audio (16bit or 24bit) streams

primer fpga esp32 altera iir i2s tang anlogic sipeed crossover-filter biquad-filter cyclone4 linkwitz-riley

Updated May 13, 2024
C++

proboterror / ZX_BUS_Mouse

Star

ZX BUS Kempston Mouse Controller

zxspectrum avr vhdl zx-spectrum altera atmega

Updated May 3, 2024
C

leonow32 / verilog-fpga

Star

Many peripherals in Verilog ready to use

fpga verilog xilinx altera systemverilog lattice cpld machxo2 machxo

Updated Jun 8, 2024
Verilog

obiwanjacobi / Zalt

Star

Zalt is a home brew Z80 computer with a modern(isch) chipset.

c z80 z80asm altera kicad cpld quartus psoc5lp wincupl

Updated Apr 17, 2024
C

BrianHGinc / BrianHG-DDR3-Controller

Star

DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

fpga intel verilog xilinx altera systemverilog lattice hdl testbenches ddr3

Updated Apr 8, 2024
SystemVerilog

jagumiel / Data-Acquisition

Star

This repository contains some examples of data acquisition over MATLAB, LabVIEW and VHDL.

arduino fpga hardware i2c data-acquisition spi altera pwm vhdl-code vhdl-examples pwm-controller

Updated Apr 4, 2024
C

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altera

Here are 186 public repositories matching this topic...

QuestIO42 / vlab

hdl-modules / hdl-modules

Charlie-Ramirez-Animation-Studios-de-MX / VHDL-Basicos

PyFPGA / pyfpga

ua1arn / hftrx

pConst / basic_verilog

f32c / f32c

drandyhaas / Haasoscope

robseb / meta-intelfpga

TanumaHideki / ReLM-PoC

otaviocmaciel / 7-segment-VHDL

MJoergen / HyperRAM

otaviocmaciel / DAC-MCP482x-VHDL-core

olofk / edalize

har-in-air / FPGA_STEREO_CROSSOVER

proboterror / ZX_BUS_Mouse

leonow32 / verilog-fpga

obiwanjacobi / Zalt

BrianHGinc / BrianHG-DDR3-Controller

jagumiel / Data-Acquisition

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