Upgrade MMU cache to 8×2 set-associative

[jserv]

This implements 8-set × 2-way set-associative cache for both load and store operations, replacing the previous direct-mapped design. This provides better hit rates while maintaining code simplicity.

• Load cache: 65% → 98% hit rate (2-entry → 8×2 set-associative)
• Store cache: 83% → 99% hit rate (1-entry → 8×2 set-associative)
• 3-bit parity hash for even distribution across 8 sets
• Simple 1-bit LRU for replacement policy
• 94% reduction in store cache misses

Memory cost: +512 bytes per hart (256B for load + 256B for store)

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Summary by cubic

Upgraded MMU load/store caches to 8-set, 2-way set-associative. This raises hit rates (load 65→98%, store 83→99%) and cuts store misses by 94%.

• New Features
  • 3-bit parity hash indexing and 1-bit LRU replacement in the MMU caches.
  • Invalidation resets all sets/ways; stats aggregate per set/way. SIGINT/SIGTERM (when MMU_CACHE_STATS is enabled) defers printing via an async-signal-safe flag and exits.
  • Recalibrated timer coefficient to 1.744e8; optional SEMU_TIMER_STATS prints calibration data.
  • Memory cost: +512 B per hart (256B load + 256B store).

^{Written for commit c7728b8. Summary will update automatically on new commits.}

[jserv]

Cc. @yy214123