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RFC: Platform-specific exception codes #146

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SoulSharer opened this issue Oct 9, 2023 · 2 comments
Open

RFC: Platform-specific exception codes #146

SoulSharer opened this issue Oct 9, 2023 · 2 comments

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@SoulSharer
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SoulSharer commented Oct 9, 2023

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Are there any plans to provide support for platform specific extensions in riscv crate?
Reading through RISC-V Privileged Architectures specification I see that there are cases where, for example, a 3.1.15 Machine Cause Register has exception codes allocated for platform and custom use.

Was wondering if it would be possible to extend enums Interrupt and Exception from outside of the riscv crate itself.
The best I could came up thus far is adding "PlatformSpecific1-32" fields to Interrupt and creating a user-defined enum PlatformInterrupt with conversion between (TryFrom<Interrupt> for PlaftormInterrupt) where applicable. (same goes for Exception)

@romancardenas
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Hi! I don't think we have plans to add this functionality right now. If you think this feature is useful, feel free to open a PR/RFC and we can discuss it further :)

In my opinion, we should look at how cortex-m deals with platform-specific interrupts and follow their approach.

@romancardenas romancardenas changed the title Platform specific extensions RFC: Platform-specific exception codes May 4, 2024
@romancardenas
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While working on #200, I've been thinking on how to provide this functionality. I propose the following approach:

  • Remove weak symbols in linker file (i.e., the PROVIDE directives) for interrupt and exception sources
  • Provide procedural macros for defining the interrupt and exception sources of a platform. These macros would be in charge of generating all the symbols related to interrupts and exceptions (e.g., _start_trap_rust, __INTERRUPTS, __EXCEPTIONS, _vector_table...). Additionally, the code will provide weak symbols to all these interrupts using global inline assembly.
  • By default, riscv-rt will use this new macro to generate a code that would be equivalent to its current version. I expect this change not to be a breaking change.
  • A new feature would be able to opt-out the standard implementation. In this way, a new my-riscv-specific-rt runtime crate would have riscv-rt as a dependency, re-exporting everything and calling to the interrupt macro accordingly to the exception codes of the target.

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