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PipelinedProcessorPatterson.qsf
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PipelinedProcessorPatterson.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2018 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
# Date created = 20:14:12 September 15, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# ARKI_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
# PROJECT SETTINGS
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE22F17C6
set_global_assignment -name TOP_LEVEL_ENTITY processor_arm
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:14:12 SEPTEMBER 15, 2019"
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files/pipelined
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH processor_tb -section_id eda_simulation
# PROJECT FILES
set_global_assignment -name SYSTEMVERILOG_FILE source/components/sl2/sl2.sv
set_global_assignment -name SYSTEMVERILOG_FILE source/components/adder/adder.sv
set_global_assignment -name SYSTEMVERILOG_FILE source/components/flopr/flopr.sv
set_global_assignment -name SYSTEMVERILOG_FILE source/components/flopr/flopr_tb.sv
set_global_assignment -name SYSTEMVERILOG_FILE source/components/signext/signext.sv
set_global_assignment -name SYSTEMVERILOG_FILE source/components/signext/signext_tb.sv
set_global_assignment -name SYSTEMVERILOG_FILE source/components/alu/alu.sv
set_global_assignment -name SYSTEMVERILOG_FILE source/components/alu/alu_tb.sv
set_global_assignment -name SYSTEMVERILOG_FILE source/components/imem/imem.sv
set_global_assignment -name SYSTEMVERILOG_FILE source/components/imem/imem_tb.sv
set_global_assignment -name SYSTEMVERILOG_FILE source/stages/maindec/maindec.sv
set_global_assignment -name SYSTEMVERILOG_FILE source/stages/maindec/maindec_tb.sv
set_global_assignment -name SYSTEMVERILOG_FILE source/stages/fetch/fetch.sv
set_global_assignment -name SYSTEMVERILOG_FILE source/stages/fetch/fetch_tb.sv
set_global_assignment -name SYSTEMVERILOG_FILE source/components/mux2/mux2.sv
set_global_assignment -name SYSTEMVERILOG_FILE source/components/mux2/mux2_tb.sv
set_global_assignment -name SYSTEMVERILOG_FILE source/stages/execute/execute.sv
set_global_assignment -name SYSTEMVERILOG_FILE source/stages/execute/execute_tb.sv
# PROJECT TEST-BENCHES
set_global_assignment -name EDA_TEST_BENCH_NAME imem_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id imem_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME imem_tb -section_id imem_tb
set_global_assignment -name EDA_TEST_BENCH_NAME regfile_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id regfile_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME regfile_tb -section_id regfile_tb
set_global_assignment -name EDA_TEST_BENCH_NAME maindec_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id maindec_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME maindec_tb -section_id maindec_tb
set_global_assignment -name EDA_TEST_BENCH_NAME fetch_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id fetch_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME fetch_tb -section_id fetch_tb
set_global_assignment -name EDA_TEST_BENCH_NAME flopr_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id flopr_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME flopr_tb -section_id flopr_tb
set_global_assignment -name EDA_TEST_BENCH_NAME mux2_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id mux2_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME mux2_tb -section_id mux2_tb
set_global_assignment -name EDA_TEST_BENCH_NAME execute_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id execute_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME execute_tb -section_id execute_tb
set_global_assignment -name EDA_TEST_BENCH_NAME processor_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id processor_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME processor_tb -section_id processor_tb
set_global_assignment -name EDA_TEST_BENCH_NAME signext_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id signext_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME signext_tb -section_id signext_tb
set_global_assignment -name EDA_TEST_BENCH_NAME alu_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id alu_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME alu_tb -section_id alu_tb
# PipelinedProcessorPatterson Files
set_global_assignment -name SYSTEMVERILOG_FILE "source/PipelinedProcessorPatterson-Modules/regfile/regfile.sv"
set_global_assignment -name SYSTEMVERILOG_FILE "source/PipelinedProcessorPatterson-Modules/regfile/regfile_tb.sv"
set_global_assignment -name SYSTEMVERILOG_FILE "source/PipelinedProcessorPatterson-Modules/aludec.sv"
set_global_assignment -name SYSTEMVERILOG_FILE "source/PipelinedProcessorPatterson-Modules/controller.sv"
set_global_assignment -name SYSTEMVERILOG_FILE "source/PipelinedProcessorPatterson-Modules/datapath.sv"
set_global_assignment -name SYSTEMVERILOG_FILE "source/PipelinedProcessorPatterson-Modules/decode.sv"
set_global_assignment -name VHDL_FILE "source/PipelinedProcessorPatterson-Modules/dmem.vhd"
set_global_assignment -name SYSTEMVERILOG_FILE "source/PipelinedProcessorPatterson-Modules/memory.sv"
set_global_assignment -name SYSTEMVERILOG_FILE "source/PipelinedProcessorPatterson-Modules/processor_arm.sv"
set_global_assignment -name SYSTEMVERILOG_FILE "source/PipelinedProcessorPatterson-Modules/processor_tb.sv"
set_global_assignment -name SYSTEMVERILOG_FILE "source/PipelinedProcessorPatterson-Modules/writeback.sv"
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name EDA_NETLIST_WRITER_OUTPUT_DIR simulation/modelsim/pipelined -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_FILE source/components/imem/imem_tb.sv -section_id imem_tb
set_global_assignment -name EDA_TEST_BENCH_FILE source/components/regfile/regfile_tb.sv -section_id regfile_tb
set_global_assignment -name EDA_TEST_BENCH_FILE source/stages/maindec/maindec_tb.sv -section_id maindec_tb
set_global_assignment -name EDA_TEST_BENCH_FILE source/stages/fetch/fetch_tb.sv -section_id fetch_tb
set_global_assignment -name EDA_TEST_BENCH_FILE source/components/flopr/flopr_tb.sv -section_id flopr_tb
set_global_assignment -name EDA_TEST_BENCH_FILE source/components/mux2/mux2_tb.sv -section_id mux2_tb
set_global_assignment -name EDA_TEST_BENCH_FILE source/stages/execute/execute_tb.sv -section_id execute_tb
set_global_assignment -name EDA_TEST_BENCH_FILE "source/PipelinedProcessorPatterson-Modules/processor_tb.sv" -section_id processor_tb
set_global_assignment -name EDA_TEST_BENCH_FILE source/components/signext/signext_tb.sv -section_id signext_tb
set_global_assignment -name EDA_TEST_BENCH_FILE source/components/alu/alu_tb.sv -section_id alu_tb
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top