eep6174: add CTL dumping support

Add support for Conformance Test Limit (CTL) data dumping. QCA6174
utilizes the same CTL storage scheme as AR93xx and QCA988x, just at
another offsets. So reuse existing dumping routine.

Capability flags location is still unknown so dump both 2GHz and 5GHz
bands since we have no option to check for really supported bands.

Author: rsa9000

eep_6174.c

@@ -99,10 +99,28 @@ static void eep_6174_dump_base_header(struct atheepmgr *aem)
 
 static void eep_6174_dump_power_info(struct atheepmgr *aem)
 {
+#define PR_CTL(__pref, __band, __is_2g)					\
+	do {								\
+		EEP_PRINT_SUBSECT_NAME(__pref " CTL data");		\
+		ar9300_dump_ctl(eep->ctlIndex ## __band,		\
+				(uint8_t *)eep->ctlFreqBin ## __band,	\
+				(uint8_t *)eep->ctlData ## __band,	\
+				QCA6174_NUM_ ## __band ## _CTLS,	\
+				QCA6174_NUM_ ## __band ## _BAND_EDGES,	\
+				__is_2g);				\
+	} while (0);
+
 	const struct eep_6174_priv *emp = aem->eepmap_priv;
 	const struct qca6174_eeprom *eep = &emp->eep;
 
 	EEP_PRINT_SECT_NAME("EEPROM Power Info");
+
+	if (1)	/* TODO: 2GHz support test */
+		PR_CTL("2 GHz", 2G, 1);
+	if (1)	/* TODO: 5GHz support test */
+		PR_CTL("5 GHz", 5G, 0);
+
+#undef PR_CTL
 }
 
 const struct eepmap eepmap_6174 = {

eep_6174.h

@@ -19,6 +19,11 @@
 
 #define QCA6174_CUSTOMER_DATA_SIZE		20
 
+#define QCA6174_NUM_2G_CTLS			18
+#define QCA6174_NUM_2G_BAND_EDGES		4
+#define QCA6174_NUM_5G_CTLS			18
+#define QCA6174_NUM_5G_BAND_EDGES		8
+
 struct qca6174_base_eep_hdr {
 	uint16_t length;
 	uint16_t checksum;
@@ -32,7 +37,21 @@ struct qca6174_base_eep_hdr {
 struct qca6174_eeprom {
 	struct qca6174_base_eep_hdr baseEepHeader;
 
-	uint8_t __unkn_0040[8060]; /* to match structure size to the EEPROM data size */
+	uint8_t __unkn_0040[2008];
+
+	uint8_t ctlIndex2G[QCA6174_NUM_2G_CTLS];
+	uint8_t __pad_082a[2];
+	uint8_t ctlFreqBin2G[QCA6174_NUM_2G_CTLS][QCA6174_NUM_2G_BAND_EDGES];
+	uint8_t ctlData2G[QCA6174_NUM_2G_CTLS][QCA6174_NUM_2G_BAND_EDGES];
+
+	uint8_t __unkn_08bc[3766];
+
+	uint8_t ctlIndex5G[QCA6174_NUM_5G_CTLS];
+	uint8_t __pad_1784[4];
+	uint8_t ctlFreqBin5G[QCA6174_NUM_5G_CTLS][QCA6174_NUM_5G_BAND_EDGES];
+	uint8_t ctlData5G[QCA6174_NUM_5G_CTLS][QCA6174_NUM_5G_BAND_EDGES];
+
+	uint8_t __unkn_18a8[1812]; /* to match structure size to the EEPROM data size */
 } __attribute__ ((packed));
 
 /* Structure size watchdog */