Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

RK3568 fails to set the sdmmc2 as the SD boot device #86

Open
Ean-cai opened this issue Nov 13, 2024 · 0 comments
Open

RK3568 fails to set the sdmmc2 as the SD boot device #86

Ean-cai opened this issue Nov 13, 2024 · 0 comments

Comments

@Ean-cai
Copy link

Ean-cai commented Nov 13, 2024

As we know, rk3568 uses the sdmmc0(dwmmc@fe2b0000) as the default SD boot device.
But now, I have to use the sdmmc2(dwmmc@fe000000) as a SD boot device.
I have tried, the sdmmc2 as a SD device is working at rootfs and uboot.
But, it can not as a SD boot device, it is timeout when sends the CMD51 in SPL.
The logs as bellow, you can see it sends the CMD timeout in SPL, but it communicates in uboot successfully.

DDR fdeec6f4fc typ 23/09/25-19:41:25,fwver: v1.19
In
LP4/4x derate en, other dram:1x trefi
SRX
ddrconfig:0
LPDDR4, 324MHz
BW=32 Col=10 Bk=8 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
tdqss: cs0 dqs0: -24ps, dqs1: -120ps, dqs2: -48ps, dqs3: -168ps,

change to: 324MHz
clk skew:0x63

change to: 528MHz
clk skew:0x58

change to: 780MHz
clk skew:0x58

change to: 1560MHz(final freq)
PHY drv:clk:38,ca:38,DQ:30,odt:60
vrefinner:16%, vrefout:29%
dram drv:40,odt:80
vref_ca:00000068
clk skew:0x21
cs 0:
the read training result:
DQS0:0x33, DQS1:0x33, DQS2:0x36, DQS3:0x2c,
min  :0x11 0x12 0x15 0x11  0x3  0x7  0xb  0x5 , 0xd  0x9  0x4  0x2  0xd  0xb  0xd  0x7 ,
      0x15 0x15  0xf  0xd  0x3  0x2  0x4  0x5 , 0xc  0x9  0x7  0x2  0xd  0xf  0x9  0xd ,
mid  :0x2a 0x2b 0x2e 0x2a 0x1c 0x20 0x24 0x1f ,0x27 0x25 0x1e 0x1d 0x28 0x26 0x27 0x23 ,
      0x2e 0x2e 0x27 0x26 0x1d 0x1c 0x1d 0x1f ,0x25 0x21 0x20 0x1b 0x26 0x27 0x23 0x27 ,
max  :0x44 0x44 0x47 0x44 0x36 0x3a 0x3d 0x39 ,0x42 0x42 0x38 0x39 0x43 0x42 0x42 0x3f ,
      0x48 0x48 0x3f 0x40 0x37 0x36 0x37 0x39 ,0x3f 0x39 0x39 0x35 0x3f 0x3f 0x3d 0x42 ,
range:0x33 0x32 0x32 0x33 0x33 0x33 0x32 0x34 ,0x35 0x39 0x34 0x37 0x36 0x37 0x35 0x38 ,
      0x33 0x33 0x30 0x33 0x34 0x34 0x33 0x34 ,0x33 0x30 0x32 0x33 0x32 0x30 0x34 0x35 ,
the write training result:
DQS0:0x1d, DQS1:0xa, DQS2:0x18, DQS3:0x0,
min  :0x64 0x67 0x67 0x66 0x55 0x57 0x5c 0x5b 0x5a ,0x4d 0x4b 0x45 0x47 0x51 0x4d 0x4f 0x4d 0x48 ,
      0x5f 0x5e 0x58 0x58 0x51 0x4d 0x50 0x54 0x56 ,0x47 0x47 0x44 0x42 0x4d 0x4b 0x47 0x4d 0x44 ,
mid  :0x7e 0x80 0x82 0x7f 0x6f 0x71 0x76 0x74 0x74 ,0x69 0x67 0x5f 0x61 0x6b 0x67 0x68 0x67 0x62 ,
      0x7b 0x7a 0x74 0x74 0x6b 0x67 0x69 0x6e 0x71 ,0x64 0x61 0x5d 0x5b 0x67 0x67 0x60 0x69 0x5d ,
max  :0x98 0x9a 0x9d 0x99 0x8a 0x8c 0x91 0x8e 0x8e ,0x86 0x83 0x79 0x7b 0x86 0x82 0x82 0x82 0x7d ,
      0x98 0x97 0x90 0x91 0x86 0x82 0x83 0x88 0x8c ,0x81 0x7b 0x77 0x75 0x82 0x83 0x7a 0x86 0x76 ,
range:0x34 0x33 0x36 0x33 0x35 0x35 0x35 0x33 0x34 ,0x39 0x38 0x34 0x34 0x35 0x35 0x33 0x35 0x35 ,
      0x39 0x39 0x38 0x39 0x35 0x35 0x33 0x34 0x36 ,0x3a 0x34 0x33 0x33 0x35 0x38 0x33 0x39 0x32 ,
CA Training result:
cs:0 min  :0x48 0x40 0x3a 0x31 0x3a 0x30 0x3c ,0x49 0x3d 0x3d 0x33 0x3e 0x33 0x3d ,
cs:0 mid  :0x82 0x83 0x76 0x72 0x74 0x71 0x68 ,0x84 0x7f 0x77 0x73 0x78 0x73 0x6a ,
cs:0 max  :0xbd 0xc6 0xb2 0xb3 0xaf 0xb2 0x94 ,0xc0 0xc2 0xb2 0xb3 0xb2 0xb3 0x97 ,
cs:0 range:0x75 0x86 0x78 0x82 0x75 0x82 0x58 ,0x77 0x85 0x75 0x80 0x74 0x80 0x5a ,
out
preloader: enable=1, addr=0xfe660000, baudrate=115200, id=2
U-Boot SPL board init
U-Boot SPL 2017.09 V130330 (Nov 08 2024 - 09:41:24)
### cpu init done
###sdmmc pwr en
###dwmci_setup_bus: set clken low pwr
unknown raw ID 0 0 0
unrecognized JEDEC id bytes: 00, 00, 00
Trying to boot from MMC2           /* ----> I set the sdmmc2 (fe000000) as the MMC2 */
###loader image start
### spl_load_image start
Buswidth = 1, clock: 0
Buswidth = 1, clock: 400000
###dwmci_setup_bus: set clken low pwr
Buswidth = 1, clock: 400000
###dwmci_setup_bus: set clken low pwr
Sending CMD0
Sending CMD8
Sending CMD55
Sending CMD41
Sending CMD55
Sending CMD41
Sending CMD55
Sending CMD41
Sending CMD55
Sending CMD41
Sending CMD55
Sending CMD41
Sending CMD55
Sending CMD41
Sending CMD55
Sending CMD41
Sending CMD55
Sending CMD41
Sending CMD55
Sending CMD41
Sending CMD55
Sending CMD41
Sending CMD55
Sending CMD41
Sending CMD55
Sending CMD41
Sending CMD55
Sending CMD41
Sending CMD55
Sending CMD41
Sending CMD55
Sending CMD41
Sending CMD55
Sending CMD41
Sending CMD55
Sending CMD41
Sending CMD55
Sending CMD41
Sending CMD55
Sending CMD41
Sending CMD55
Sending CMD41
Sending CMD55
Sending CMD41
Sending CMD55
Sending CMD41
Sending CMD55
Sending CMD41
Sending CMD55
Sending CMD41
Sending CMD55
Sending CMD41
Sending CMD55
Sending CMD41
Sending CMD55
Sending CMD41
Sending CMD55
Sending CMD41
Sending CMD55
Sending CMD41
Sending CMD55
Sending CMD41
Sending CMD55
Sending CMD41
Sending CMD55
Sending CMD41
Sending CMD55
Sending CMD41
Sending CMD55
Sending CMD41
Sending CMD55
Sending CMD41
Sending CMD55
Sending CMD41
Sending CMD55
Sending CMD41
Sending CMD55
Sending CMD41
Sending CMD55
Sending CMD41
Sending CMD55
Sending CMD41
Sending CMD55
Sending CMD41
Sending CMD55
Sending CMD41
Sending CMD55
Sending CMD41
Sending CMD55
Sending CMD41
Sending CMD2
Sending CMD3
Sending CMD9
Sending CMD7
Sending CMD55
Sending CMD51
###drto_clks: 16777215
###drto_div: 0
###drto_ms: 41944
###dwmci_get_drto add spare time         
dwmci_data_transfer: Timeout waiting for data!
Sending CMD51
dwmci_send_cmd: Response Timeout.   /* ----> Sending CMD51 timeout in SPL stage*/
Sending CMD51
dwmci_send_cmd: Response Timeout.
Sending CMD51
dwmci_send_cmd: Response Timeout.
MMC error: The cmd index is 51, ret is -110
Sending CMD51
dwmci_send_cmd: Response Timeout.
Sending CMD51
dwmci_send_cmd: Response Timeout.
Sending CMD51
dwmci_send_cmd: Response Timeout.
Sending CMD51
dwmci_send_cmd: Response Timeout.
MMC error: The cmd index is 51, ret is -110
Sending CMD51
dwmci_send_cmd: Response Timeout.
Sending CMD51
dwmci_send_cmd: Response Timeout.
Sending CMD51
dwmci_send_cmd: Response Timeout.
Sending CMD51
dwmci_send_cmd: Response Timeout.
MMC error: The cmd index is 51, ret is -110
Sending CMD51
dwmci_send_cmd: Response Timeout.
Sending CMD51
dwmci_send_cmd: Response Timeout.
Sending CMD51
dwmci_send_cmd: Response Timeout.
Sending CMD51
dwmci_send_cmd: Response Timeout.
MMC error: The cmd index is 51, ret is -110
mmc_init: -110, time 42216
spl: mmc init failed with error: -110
###loader image done
Trying to boot from MMC1
###loader image start
### spl_load_image start
### mmc init done
SPL: A/B-slot: _b, successful: 0, tries-remain: 7
Trying fit image at 0x4000 sector
## Verified-boot: 0
board_fit_config_name_match: rk3568-rom5880a1
board_fit_config_name_match: rk3568-rom5880a1
## Checking atf-1 0x00040000 ... sha256(b5946ac63d...) + OK
board_fit_config_name_match: rk3568-rom5880a1
## Checking uboot 0x00a00000 ... sha256(144c73b862...) + OK
board_fit_config_name_match: rk3568-rom5880a1
## Checking fdt 0x00b48408 ... sha256(944ff5d5c1...) + OK
board_fit_config_name_match: rk3568-rom5880a1
board_fit_config_name_match: rk3568-rom5880a1
board_fit_config_name_match: rk3568-rom5880a1
board_fit_config_name_match: rk3568-rom5880a1
## Checking atf-2 0xfdcc1000 ... sha256(b8dca786b4...) + OK
board_fit_config_name_match: rk3568-rom5880a1
board_fit_config_name_match: rk3568-rom5880a1
board_fit_config_name_match: rk3568-rom5880a1
## Checking atf-3 0x0006b000 ... sha256(2f91089eb7...) + OK
board_fit_config_name_match: rk3568-rom5880a1
board_fit_config_name_match: rk3568-rom5880a1
board_fit_config_name_match: rk3568-rom5880a1
## Checking atf-4 0xfdcce000 ... sha256(86ef885748...) + OK
board_fit_config_name_match: rk3568-rom5880a1
board_fit_config_name_match: rk3568-rom5880a1
board_fit_config_name_match: rk3568-rom5880a1
## Checking atf-5 0xfdcd0000 ... sha256(0b2b146c60...) + OK
board_fit_config_name_match: rk3568-rom5880a1
board_fit_config_name_match: rk3568-rom5880a1
board_fit_config_name_match: rk3568-rom5880a1
## Checking atf-6 0x00069000 ... sha256(a9a1e63bef...) + OK
board_fit_config_name_match: rk3568-rom5880a1
board_fit_config_name_match: rk3568-rom5880a1
board_fit_config_name_match: rk3568-rom5880a1
## Checking optee 0x08400000 ... sha256(6c92ef6a0e...) + OK
board_fit_config_name_match: rk3568-rom5880a1
board_fit_config_name_match: rk3568-rom5880a1
board_fit_config_name_match: rk3568-rom5880a1
### loader image fail
Jumping to U-Boot(0x00a00000) via ARM Trusted Firmware(0x00040000)
Total: 42507.945/42781.414 ms

INFO:    Preloader serial: 2
NOTICE:  BL31: v2.3():v2.3-645-g8cea6ab0b:cl, fwver: v1.44
NOTICE:  BL31: Built : 16:36:43, Sep 19 2023
INFO:    GICv3 without legacy support detected.
INFO:    ARM GICv3 driver initialized in EL3
INFO:    pmu v1 is valid 220114
INFO:    l3 cache partition cfg-0
INFO:    dfs DDR fsp_param[0].freq_mhz= 1560MHz
INFO:    dfs DDR fsp_param[1].freq_mhz= 324MHz
INFO:    dfs DDR fsp_param[2].freq_mhz= 528MHz
INFO:    dfs DDR fsp_param[3].freq_mhz= 780MHz
INFO:    Using opteed sec cpu_context!
INFO:    boot cpu mask: 0
INFO:    BL31: Initializing runtime services
INFO:    BL31: Initializing BL32
I/TC:
I/TC: OP-TEE version: 3.13.0-743-gb5340fd65 #hisping.lin (gcc version 10.2.1 20201103 (GNU Toolchain for the A-profile Architecture 10.2-2020.11 (arm-10.16))) #5 Mon Aug 28 15:15:17 CST 2023 aarch64
I/TC: Primary CPU initializing
E/TC:0 0 hal_algo_version_init:296 CRYPTO_CRYPTO_VERSION_NEW no support. Skip all algo mode check.
I/TC: Primary CPU switching to normal world boot
INFO:    BL31: Preparing for EL3 exit to normal world
INFO:    Entry point address = 0xa00000
INFO:    SPSR = 0x3c9


U-Boot 2017.09 V130330 (Nov 08 2024 - 09:41:24 +0800)

Model: Advantech RK3568 ROM5880 Board
MPIDR: 0x81000000
PreSerial: 2, raw, 0xfe660000
DRAM:  2 GiB
Sysmem: init
Relocation Offset: 7d217000
Relocation fdt: 7b9f90e8 - 7b9fece0
CR: M/C/I
Hotkey: ctrl+c
optee api revision: 2.0
###sdmmc pwr en
###dwmci_setup_bus: set clken low pwr
###sdmmc pwr en
###sdmmc pwr en
###dwmci_setup_bus: set clken low pwr
dwmmc@fe000000: 1, dwmmc@fe2b0000: 3, dwmmc@fe2c0000: 2, sdhci@fe310000: 0
Bootdev(atags): mmc 0    
MMC0: HS200, 200Mhz
PartType: EFI
TEEC: Waring: Could not find security partition
DM: v1
boot mode: normal
RESC: 'boot', blk@0x0001b240
resource: sha256+
FIT: no signed, no conf required
DTB: rk-kernel.dtb
HASH(c): OK
swversion = V130330
Read board id : 0,  adcval = 1023
rk3568_pmuclk_set_rate 5 32768
rk3568_pmuclk_set_rate 1 200000000
rk3568_pmuclk_set_rate 43 100000000
I2c0 speed: 100000Hz
rk3568_pmuclk_get_rate 7
vsel-gpios- not found! Error: -2
vdd_cpu 1000000 uV
PMIC:  RK8090 (on=0x80, off=0x00)
vdd_logic init 900000 uV
vdd_gpu init 900000 uV
vdd_npu init 900000 uV
io-domain: OK
INFO:    ddr dmc_fsp already initialized in loader.
Could not find baseparameter partition
Model: ROM-5880 AKK4973193 V130330 A1
MPIDR: 0x81000000
Device 'gpio@fdd60000': seq 0 is in use by 'gpio0@fdd60000'
Device 'gpio@fe740000': seq 1 is in use by 'gpio@fdd60000'
Device 'gpio@fe750000': seq 2 is in use by 'gpio@fe740000'
Device 'gpio@fe760000': seq 3 is in use by 'gpio@fe750000'
## Error: Can't overwrite "ethaddr"
## Error inserting "ethaddr" variable, errno=1
## Error: Can't overwrite "eth1addr"
## Error inserting "eth1addr" variable, errno=1
** File not found logo.bmp **
Failed ext4load mmc 0:7 0x000000007bd9ca90 logo.bmp 200Rockchip UBOOT DRM driver version: v1.0.1
VOP have 1 active VP
vp0 have layer nr:6[0 2 4 1 3 5 ], primary plane: 4
vp1 have layer nr:0[], primary plane: 0
vp2 have layer nr:0[], primary plane: 0
hdmi@fe0a0000 disconnected
CLK: (sync kernel. arm: enter 816000 KHz, init 816000 KHz, kernel 0N/A)
  apll 1104000 KHz
  dpll 780000 KHz
  gpll 1188000 KHz
  cpll 1000000 KHz
  npll 1200000 KHz
  vpll 24000 KHz
rk3568_pmuclk_get_rate 2
  hpll 24000 KHz
rk3568_pmuclk_get_rate 1
  ppll 200000 KHz
  armclk 1104000 KHz
  aclk_bus 150000 KHz
  pclk_bus 100000 KHz
  aclk_top_high 500000 KHz
  aclk_top_low 400000 KHz
  hclk_top 150000 KHz
  pclk_top 100000 KHz
  aclk_perimid 300000 KHz
  hclk_perimid 150000 KHz
rk3568_pmuclk_get_rate 43
  pclk_pmu 100000 KHz
Net:   FEC: can't find phy-handle
eth0: ethernet@fe2a0000FEC: can't find phy-handle
, eth1: ethernet@fe010000
Hit key to stop autoboot('CTRL+C'):  0
=> mmc list
dwmmc@fe000000: 1
dwmmc@fe2b0000: 3
dwmmc@fe2c0000: 2
sdhci@fe310000: 0 (eMMC)
=> mmc dev 1                     /* ----> Using the sdmmc2 (fe000000)*/
Buswidth = 1, clock: 0
Buswidth = 1, clock: 400000
###dwmci_setup_bus: set clken low pwr
Buswidth = 1, clock: 400000
###dwmci_setup_bus: set clken low pwr
Sending CMD0
Sending CMD8
Sending CMD55
Sending CMD41
Sending CMD55
Sending CMD41
Sending CMD55
Sending CMD41
Sending CMD55
Sending CMD41
Sending CMD2
Sending CMD3
Sending CMD9
Sending CMD7
Sending CMD55
Sending CMD51
Sending CMD6
Sending CMD6
Sending CMD55
Sending CMD6
Buswidth = 4, clock: 400000
###dwmci_setup_bus: set clken low pwr
Sending CMD55
Sending CMD13
Buswidth = 4, clock: 52000000
###dwmci_setup_bus: set clken low pwr
Sending CMD16
Sending CMD17
Sending CMD16
Sending CMD17
Sending CMD16
Sending CMD17
Sending CMD16
Sending CMD18
Sending CMD12
Sending CMD16
Sending CMD17
Sending CMD16
Sending CMD17
Sending CMD16
Sending CMD18
Sending CMD12
switch to partitions #0, OK    /* ----> Communicating successfully in uboot stage*/
mmc1 is current device
=>

Finally, I know the reson why it sends CMD timeout in SPL.
The sdmmc0 is set to secure, but the sdmmc2 is not set to secure.
The code as bellow.

int arch_cpu_init(void)
{
#ifdef CONFIG_SPL_BUILD
	/*
	 * When perform idle operation, corresponding clock can
	 * be opened or gated automatically.
	 */
	writel(0xffffffff, PMU_BASE_ADDR + PMU_NOC_AUTO_CON0);
	writel(0x000f000f, PMU_BASE_ADDR + PMU_NOC_AUTO_CON1);

	/* Set the emmc sdmmc0 to secure */
	writel(((0x3 << 11 | 0x1 << 4) << 16), SGRF_BASE + SGRF_SOC_CON4);
......

And, I can not find more about the SGRF on the TRM.
So, can you help me how to set the sdmmc2 to secure?
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Assignees
No one assigned
Labels
None yet
Projects
None yet
Milestone
No milestone
Development

No branches or pull requests
1 participant
@Ean-cai