Zynq-7000 peripheral limitations?

[shareefj]

Description

I'm starting to bring up some software on a Zynq-7000 platform and am running into some issues with unimplemented registers. The first case seems to be when setting up the UART and reading the SLCR.UART_CLK_CTRL register. I haven't debugged the issue fully but I think I'm seeing a panic from a divide by zero.

I get the following read/write warnings to the log:

07:23:45.2192 [WARNING] scu: Unhandled write to offset 0xC, value 0xFFFF.
07:23:45.2597 [WARNING] scu: Unhandled write to offset 0x0. Unhandled bits: [3] when writing value 0x9. Tags: Speculative linefills enable (0x1).
07:23:45.2683 [WARNING] cpu: Unknown CP15 32-bit write - op1=0, crn=1, crm=0, op2=1 (2)
07:23:45.2721 [WARNING] slcr: Unhandled write to offset 0x7C0, value 0x12E0.
07:23:45.2723 [WARNING] slcr: Unhandled write to offset 0x7C4, value 0x12E1.
07:23:45.2725 [WARNING] slcr: Unhandled read from offset 0x228.
07:23:45.2726 [WARNING] slcr: Unhandled write to offset 0x228, value 0x5.
07:23:45.2728 [WARNING] slcr: Unhandled read from offset 0x228.
07:23:45.2729 [WARNING] slcr: Unhandled write to offset 0x228, value 0x0.
07:23:45.2738 [WARNING] slcr: Unhandled read from offset 0x154.
07:23:45.2740 [WARNING] slcr: Unhandled write to offset 0x154, value 0x1402.

The others are UART MIO pin configuration settings but they don't matter. What should I be doing with the clock control register?

What other limitations should users be aware of?

Thanks.

[mateusz-holenko]

Hi @shareefj, thanks for the question.

Renode allows users to easily mock or partially model fragments of logic necessary to drive the simulation. In this context warning log messages about unhandled writes/reads do not always indicate errors. In many cases if your software behaves correctly, those can be treated strictly informational.

Having said that, if you do observe crashes or misbehavior related to a missing functionality, the model can/should be of course improved.

For easier debugging of such situations, using function names and peripheral access logging is very useful:

(machine-0) cpu LogFunctionNames true true
(machine-0) sysbus LogAllPeripheralsAccess true

Right now, the Zynq7000 SystemLevelControlRegisters model does not implement the UART_CLK_CTRL register which means that it will be read as 0.
If you need it to return a non-zero value I would suggest looking into the BuildRegisters method and adding the necessary logic there: https://github.com/renode/renode-infrastructure/blob/master/src/Emulator/Peripherals/Peripherals/Miscellaneous/Zynq7000_SystemLevelControlRegisters.cs#L37.