diff --git a/soc/xtensa/intel_s1000/soc.c b/soc/xtensa/intel_s1000/soc.c
index e88ee07f95d1..afb7d6fd2495 100644
--- a/soc/xtensa/intel_s1000/soc.c
+++ b/soc/xtensa/intel_s1000/soc.c
@@ -186,12 +186,23 @@ u32_t soc_get_ref_clk_freq(void)
 
 static void soc_set_power_and_clock(void)
 {
-	volatile struct soc_dsp_shim_regs *regs =
-		(volatile struct soc_dsp_shim_regs *)
-		SOC_DSP_SHIM_REG_BASE;
+	volatile struct soc_dsp_shim_regs *dsp_shim_regs =
+		(volatile struct soc_dsp_shim_regs *)SOC_DSP_SHIM_REG_BASE;
+#if (CONFIG_AUDIO_INTEL_DMIC)
+	volatile struct soc_dmic_shim_regs *dmic_shim_regs =
+		(volatile struct soc_dmic_shim_regs *)SOC_DMIC_SHIM_REG_BASE;
 
-	regs->clkctl |= SOC_CLKCTL_REQ_FAST_CLK | SOC_CLKCTL_OCS_FAST_CLK;
-	regs->pwrctl |= SOC_PWRCTL_DISABLE_PWR_GATING_DSP1 |
+	/* enable power */
+	dmic_shim_regs->dmiclctl |= SOC_DMIC_SHIM_DMICLCTL_SPA;
+
+	while ((dmic_shim_regs->dmiclctl & SOC_DMIC_SHIM_DMICLCTL_CPA) == 0) {
+		/* wait for power status */
+	}
+#endif
+
+	dsp_shim_regs->clkctl |= SOC_CLKCTL_REQ_FAST_CLK |
+		SOC_CLKCTL_OCS_FAST_CLK;
+	dsp_shim_regs->pwrctl |= SOC_PWRCTL_DISABLE_PWR_GATING_DSP1 |
 		SOC_PWRCTL_DISABLE_PWR_GATING_DSP0;
 }
 
diff --git a/soc/xtensa/intel_s1000/soc.h b/soc/xtensa/intel_s1000/soc.h
index c04453eb8a50..04524bf9f5f7 100644
--- a/soc/xtensa/intel_s1000/soc.h
+++ b/soc/xtensa/intel_s1000/soc.h
@@ -117,6 +117,16 @@ struct soc_resource_alloc_regs {
 	u32_t	geno;
 };
 
+/* DMIC SHIM Registers */
+#define SOC_DMIC_SHIM_REG_BASE			0x00071E80
+#define SOC_DMIC_SHIM_DMICLCTL_SPA		BIT(0)
+#define SOC_DMIC_SHIM_DMICLCTL_CPA		BIT(8)
+
+struct soc_dmic_shim_regs {
+	u32_t	dmiclcap;
+	u32_t	dmiclctl;
+};
+
 /* SOC DSP SHIM Registers */
 #define SOC_DSP_SHIM_REG_BASE			0x00071F00
 /* SOC DSP SHIM Register - Clock Control */